db-mv784mp-gp.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <miiphy.h>
  8. #include <net.h>
  9. #include <netdev.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/soc.h>
  13. #include <linux/bitops.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #define ETH_PHY_CTRL_REG 0
  16. #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
  17. #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
  18. /*
  19. * Those values and defines are taken from the Marvell U-Boot version
  20. * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
  21. * "RD-AXP-GP rev 1.0".
  22. *
  23. * GPPs
  24. * MPP# NAME IN/OUT
  25. * ----------------------------------------------
  26. * 21 SW_Reset_ OUT
  27. * 25 Phy_Int# IN
  28. * 28 SDI_WP IN
  29. * 29 SDI_Status IN
  30. * 54-61 On GPP Connector ?
  31. * 62 Switch Interrupt IN
  32. * 63-65 Reserved from SW Board ?
  33. * 66 SW_BRD connected IN
  34. */
  35. #define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
  36. #define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
  37. #define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
  38. #define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
  39. #define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
  40. #define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
  41. int board_early_init_f(void)
  42. {
  43. /* Configure MPP */
  44. writel(0x00000000, MVEBU_MPP_BASE + 0x00);
  45. writel(0x00000000, MVEBU_MPP_BASE + 0x04);
  46. writel(0x33000000, MVEBU_MPP_BASE + 0x08);
  47. writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
  48. writel(0x11111111, MVEBU_MPP_BASE + 0x10);
  49. writel(0x00221100, MVEBU_MPP_BASE + 0x14);
  50. writel(0x00000003, MVEBU_MPP_BASE + 0x18);
  51. writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
  52. writel(0x00000000, MVEBU_MPP_BASE + 0x20);
  53. /* Configure GPIO */
  54. writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  55. writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  56. writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  57. writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  58. writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
  59. writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
  60. return 0;
  61. }
  62. int board_init(void)
  63. {
  64. /* adress of boot parameters */
  65. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  66. return 0;
  67. }
  68. int checkboard(void)
  69. {
  70. puts("Board: Marvell DB-MV784MP-GP\n");
  71. return 0;
  72. }
  73. int board_eth_init(struct bd_info *bis)
  74. {
  75. cpu_eth_init(bis); /* Built in controller(s) come first */
  76. return pci_eth_init(bis);
  77. }
  78. int board_phy_config(struct phy_device *phydev)
  79. {
  80. u16 reg;
  81. /* Enable QSGMII AN */
  82. /* Set page to 4 */
  83. phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
  84. /* Enable AN */
  85. phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
  86. /* Set page to 0 */
  87. phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
  88. /* Phy C_ANEG */
  89. reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
  90. reg |= 0x1E0;
  91. phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
  92. /* Soft-Reset */
  93. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
  94. phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
  95. /* Power up the phy */
  96. reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
  97. reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
  98. phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
  99. printf("88E1545 Initialized\n");
  100. return 0;
  101. }