db-88f6820-gp.c 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <init.h>
  8. #include <miiphy.h>
  9. #include <net.h>
  10. #include <netdev.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/soc.h>
  14. #include <linux/bitops.h>
  15. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  16. #include <../serdes/a38x/high_speed_env_spec.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /*
  19. * Those values and defines are taken from the Marvell U-Boot version
  20. * "u-boot-2013.01-2014_T3.0"
  21. */
  22. #define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
  23. (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
  24. BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
  25. BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  26. #define DB_GP_88F68XX_GPP_OUT_ENA_MID \
  27. (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
  28. BIT(16) | BIT(17) | BIT(18)))
  29. #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
  30. #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
  31. #define DB_GP_88F68XX_GPP_POL_LOW 0x0
  32. #define DB_GP_88F68XX_GPP_POL_MID 0x0
  33. /* IO expander on Marvell GP board includes e.g. fan enabling */
  34. struct marvell_io_exp {
  35. u8 chip;
  36. u8 addr;
  37. u8 val;
  38. };
  39. static struct marvell_io_exp io_exp[] = {
  40. { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
  41. { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
  42. { 0x20, 2, 0x1D }, /* Output Data, register#0 */
  43. { 0x20, 3, 0x18 }, /* Output Data, register#1 */
  44. { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
  45. { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
  46. { 0x21, 2, 0x08 }, /* Output Data, register#0 */
  47. { 0x21, 3, 0xC0 } /* Output Data, register#1 */
  48. };
  49. static struct serdes_map board_serdes_map[] = {
  50. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  51. {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  52. {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  53. {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  54. {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  55. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  56. };
  57. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  58. {
  59. *serdes_map_array = board_serdes_map;
  60. *count = ARRAY_SIZE(board_serdes_map);
  61. return 0;
  62. }
  63. /*
  64. * Define the DDR layout / topology here in the board file. This will
  65. * be used by the DDR3 init code in the SPL U-Boot version to configure
  66. * the DDR3 controller.
  67. */
  68. static struct mv_ddr_topology_map board_topology_map = {
  69. DEBUG_LEVEL_ERROR,
  70. 0x1, /* active interfaces */
  71. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  72. { { { {0x1, 0, 0, 0},
  73. {0x1, 0, 0, 0},
  74. {0x1, 0, 0, 0},
  75. {0x1, 0, 0, 0},
  76. {0x1, 0, 0, 0} },
  77. SPEED_BIN_DDR_1866L, /* speed_bin */
  78. MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
  79. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  80. MV_DDR_FREQ_800, /* frequency */
  81. 0, 0, /* cas_wl cas_l */
  82. MV_DDR_TEMP_LOW, /* temperature */
  83. MV_DDR_TIM_DEFAULT} }, /* timing */
  84. BUS_MASK_32BIT, /* Busses mask */
  85. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  86. { {0} }, /* raw spd data */
  87. {0} /* timing parameters */
  88. };
  89. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  90. {
  91. /* Return the board topology as defined in the board code */
  92. return &board_topology_map;
  93. }
  94. int board_early_init_f(void)
  95. {
  96. /* Configure MPP */
  97. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  98. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  99. writel(0x11244011, MVEBU_MPP_BASE + 0x08);
  100. writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
  101. writel(0x22200002, MVEBU_MPP_BASE + 0x10);
  102. writel(0x30042022, MVEBU_MPP_BASE + 0x14);
  103. writel(0x55550555, MVEBU_MPP_BASE + 0x18);
  104. writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
  105. /* Set GPP Out value */
  106. writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  107. writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  108. /* Set GPP Polarity */
  109. writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  110. writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  111. /* Set GPP Out Enable */
  112. writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  113. writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  114. return 0;
  115. }
  116. int board_init(void)
  117. {
  118. int i;
  119. /* adress of boot parameters */
  120. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  121. /* Init I2C IO expanders */
  122. for (i = 0; i < ARRAY_SIZE(io_exp); i++)
  123. i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
  124. return 0;
  125. }
  126. int checkboard(void)
  127. {
  128. puts("Board: Marvell DB-88F6820-GP\n");
  129. return 0;
  130. }
  131. int board_eth_init(struct bd_info *bis)
  132. {
  133. cpu_eth_init(bis); /* Built in controller(s) come first */
  134. return pci_eth_init(bis);
  135. }