db-88f6820-amc.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <init.h>
  8. #include <miiphy.h>
  9. #include <net.h>
  10. #include <netdev.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/soc.h>
  14. #include <linux/bitops.h>
  15. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  16. #include <../serdes/a38x/high_speed_env_spec.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /*
  19. * Those values and defines are taken from the Marvell U-Boot version
  20. * "u-boot-2013.01-2016_T1.0.eng_drop_v10"
  21. */
  22. #define DB_AMC_88F68XX_GPP_OUT_ENA_LOW \
  23. (~(BIT(29)))
  24. #define DB_AMC_88F68XX_GPP_OUT_ENA_MID \
  25. (~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21)))
  26. #define DB_AMC_88F68XX_GPP_OUT_VAL_LOW (BIT(29))
  27. #define DB_AMC_88F68XX_GPP_OUT_VAL_MID 0x0
  28. #define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH 0x0
  29. #define DB_AMC_88F68XX_GPP_POL_LOW 0x0
  30. #define DB_AMC_88F68XX_GPP_POL_MID 0x0
  31. static struct serdes_map board_serdes_map[] = {
  32. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  33. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  34. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  35. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  36. {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  37. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  38. };
  39. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  40. {
  41. *serdes_map_array = board_serdes_map;
  42. *count = ARRAY_SIZE(board_serdes_map);
  43. return 0;
  44. }
  45. /*
  46. * Define the DDR layout / topology here in the board file. This will
  47. * be used by the DDR3 init code in the SPL U-Boot version to configure
  48. * the DDR3 controller.
  49. */
  50. static struct mv_ddr_topology_map board_topology_map = {
  51. DEBUG_LEVEL_ERROR,
  52. 0x1, /* active interfaces */
  53. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  54. { { { {0x1, 0, 0, 0},
  55. {0x1, 0, 0, 0},
  56. {0x1, 0, 0, 0},
  57. {0x1, 0, 0, 0},
  58. {0x1, 0, 0, 0} },
  59. SPEED_BIN_DDR_1866L, /* speed_bin */
  60. MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
  61. MV_DDR_DIE_CAP_2GBIT, /* mem_size */
  62. MV_DDR_FREQ_800, /* frequency */
  63. 0, 0, /* cas_wl cas_l */
  64. MV_DDR_TEMP_LOW, /* temperature */
  65. MV_DDR_TIM_DEFAULT} }, /* timing */
  66. BUS_MASK_32BIT, /* Busses mask */
  67. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  68. { {0} }, /* raw spd data */
  69. {0} /* timing parameters */
  70. };
  71. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  72. {
  73. /* Return the board topology as defined in the board code */
  74. return &board_topology_map;
  75. }
  76. int board_early_init_f(void)
  77. {
  78. /* Configure MPP */
  79. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  80. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  81. writel(0x55066011, MVEBU_MPP_BASE + 0x08);
  82. writel(0x05055550, MVEBU_MPP_BASE + 0x0c);
  83. writel(0x05055555, MVEBU_MPP_BASE + 0x10);
  84. writel(0x01106565, MVEBU_MPP_BASE + 0x14);
  85. writel(0x40000000, MVEBU_MPP_BASE + 0x18);
  86. writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  87. /* Set GPP Out value */
  88. writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  89. writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  90. /* Set GPP Polarity */
  91. writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  92. writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  93. /* Set GPP Out Enable */
  94. writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  95. writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  96. return 0;
  97. }
  98. int board_init(void)
  99. {
  100. /* adress of boot parameters */
  101. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  102. return 0;
  103. }
  104. int checkboard(void)
  105. {
  106. puts("Board: Marvell DB-88F6820-AMC\n");
  107. return 0;
  108. }
  109. int board_eth_init(struct bd_info *bis)
  110. {
  111. cpu_eth_init(bis); /* Built in controller(s) come first */
  112. return pci_eth_init(bis);
  113. }