ucp1020.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013-2019 Arcturus Networks, Inc.
  4. * https://www.arcturusnetworks.com/products/ucp1020/
  5. * by Oleksandr G Zhadan et al.
  6. * based on board/freescale/p1_p2_rdb_pc/spl.c
  7. * original copyright follows:
  8. * Copyright 2013 Freescale Semiconductor, Inc.
  9. */
  10. #include <common.h>
  11. #include <command.h>
  12. #include <env.h>
  13. #include <hwconfig.h>
  14. #include <image.h>
  15. #include <init.h>
  16. #include <net.h>
  17. #include <pci.h>
  18. #include <i2c.h>
  19. #include <miiphy.h>
  20. #include <linux/libfdt.h>
  21. #include <fdt_support.h>
  22. #include <fsl_mdio.h>
  23. #include <tsec.h>
  24. #include <ioports.h>
  25. #include <netdev.h>
  26. #include <micrel.h>
  27. #include <spi_flash.h>
  28. #include <mmc.h>
  29. #include <linux/ctype.h>
  30. #include <asm/fsl_serdes.h>
  31. #include <asm/gpio.h>
  32. #include <asm/processor.h>
  33. #include <asm/mmu.h>
  34. #include <asm/cache.h>
  35. #include <asm/immap_85xx.h>
  36. #include <asm/fsl_pci.h>
  37. #include <fsl_ddr_sdram.h>
  38. #include <asm/io.h>
  39. #include <asm/fsl_law.h>
  40. #include <asm/fsl_lbc.h>
  41. #include <asm/mp.h>
  42. #include "ucp1020.h"
  43. void spi_set_speed(struct spi_slave *slave, uint hz)
  44. {
  45. /* TO DO: It's actially have to be in spi/ */
  46. }
  47. /*
  48. * To be compatible with cmd_gpio
  49. */
  50. int name_to_gpio(const char *name)
  51. {
  52. int gpio = 31 - simple_strtoul(name, NULL, 10);
  53. if (gpio < 16)
  54. gpio = -1;
  55. return gpio;
  56. }
  57. void board_gpio_init(void)
  58. {
  59. int i;
  60. char envname[8], *val;
  61. for (i = 0; i < GPIO_MAX_NUM; i++) {
  62. sprintf(envname, "GPIO%d", i);
  63. val = env_get(envname);
  64. if (val) {
  65. char direction = toupper(val[0]);
  66. char level = toupper(val[1]);
  67. if (direction == 'I') {
  68. gpio_direction_input(i);
  69. } else {
  70. if (direction == 'O') {
  71. if (level == '1')
  72. gpio_direction_output(i, 1);
  73. else
  74. gpio_direction_output(i, 0);
  75. }
  76. }
  77. }
  78. }
  79. val = env_get("PCIE_OFF");
  80. if (val) {
  81. gpio_direction_input(GPIO_PCIE1_EN);
  82. gpio_direction_input(GPIO_PCIE2_EN);
  83. } else {
  84. gpio_direction_output(GPIO_PCIE1_EN, 1);
  85. gpio_direction_output(GPIO_PCIE2_EN, 1);
  86. }
  87. val = env_get("SDHC_CDWP_OFF");
  88. if (!val) {
  89. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  90. setbits_be32(&gur->pmuxcr,
  91. (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
  92. }
  93. }
  94. int board_early_init_f(void)
  95. {
  96. return 0; /* Just in case. Could be disable in config file */
  97. }
  98. int checkboard(void)
  99. {
  100. printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
  101. board_gpio_init();
  102. #ifdef CONFIG_MMC
  103. printf("SD/MMC: 4-bit Mode\n");
  104. #endif
  105. return 0;
  106. }
  107. #ifdef CONFIG_PCI
  108. void pci_init_board(void)
  109. {
  110. fsl_pcie_init_board(0);
  111. }
  112. #endif
  113. int board_early_init_r(void)
  114. {
  115. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  116. const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  117. /*
  118. * Remap Boot flash region to caching-inhibited
  119. * so that flash can be erased properly.
  120. */
  121. /* Flush d-cache and invalidate i-cache of any FLASH data */
  122. flush_dcache();
  123. invalidate_icache();
  124. /* invalidate existing TLB entry for flash */
  125. disable_tlb(flash_esel);
  126. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  127. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
  128. 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
  129. return 0;
  130. }
  131. int board_phy_config(struct phy_device *phydev)
  132. {
  133. #if defined(CONFIG_PHY_MICREL_KSZ9021)
  134. int regval;
  135. static int cnt;
  136. if (cnt++ == 0)
  137. printf("PHYs address [");
  138. if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
  139. regval =
  140. ksz9021_phy_extended_read(phydev,
  141. MII_KSZ9021_EXT_STRAP_STATUS);
  142. /*
  143. * min rx data delay
  144. */
  145. ksz9021_phy_extended_write(phydev,
  146. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
  147. 0x6666);
  148. /*
  149. * max rx/tx clock delay, min rx/tx control
  150. */
  151. ksz9021_phy_extended_write(phydev,
  152. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
  153. 0xf6f6);
  154. printf("0x%x", (regval & 0x1f));
  155. } else {
  156. printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
  157. }
  158. if (cnt == 3)
  159. printf("] ");
  160. else
  161. printf(",");
  162. #endif
  163. #if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
  164. regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
  165. if (regval >= 0)
  166. printf(" (ADDR 0x%x) ", regval & 0x1f);
  167. #endif
  168. return 0;
  169. }
  170. int last_stage_init(void)
  171. {
  172. static char newkernelargs[256];
  173. static u8 id1[16];
  174. static u8 id2;
  175. #ifdef CONFIG_MMC
  176. struct mmc *mmc;
  177. #endif
  178. char *sval, *kval;
  179. if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
  180. printf("Error reading i2c IDT6V49205B information!\n");
  181. } else {
  182. printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
  183. i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
  184. if (!(id1[1] & 0x02)) {
  185. id1[1] |= 0x02;
  186. i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
  187. asm("nop; nop");
  188. }
  189. }
  190. if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
  191. printf("Error reading i2c NCT72 information!\n");
  192. else
  193. printf("NCT72(0x%x): ready\n", id2);
  194. kval = env_get("kernelargs");
  195. #ifdef CONFIG_MMC
  196. mmc = find_mmc_device(0);
  197. if (mmc)
  198. if (!mmc_init(mmc)) {
  199. printf("MMC/SD card detected\n");
  200. if (kval) {
  201. int n = strlen(defkargs);
  202. char *tmp = strstr(kval, defkargs);
  203. *tmp = 0;
  204. strcpy(newkernelargs, kval);
  205. strcat(newkernelargs, " ");
  206. strcat(newkernelargs, mmckargs);
  207. strcat(newkernelargs, " ");
  208. strcat(newkernelargs, &tmp[n]);
  209. env_set("kernelargs", newkernelargs);
  210. } else {
  211. env_set("kernelargs", mmckargs);
  212. }
  213. }
  214. #endif
  215. get_arc_info();
  216. if (kval) {
  217. sval = env_get("SERIAL");
  218. if (sval) {
  219. strcpy(newkernelargs, "SN=");
  220. strcat(newkernelargs, sval);
  221. strcat(newkernelargs, " ");
  222. strcat(newkernelargs, kval);
  223. env_set("kernelargs", newkernelargs);
  224. }
  225. } else {
  226. printf("Error reading kernelargs env variable!\n");
  227. }
  228. return 0;
  229. }
  230. int board_eth_init(struct bd_info *bis)
  231. {
  232. struct fsl_pq_mdio_info mdio_info;
  233. struct tsec_info_struct tsec_info[4];
  234. #ifdef CONFIG_TSEC2
  235. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  236. #endif
  237. int num = 0;
  238. #ifdef CONFIG_TSEC1
  239. SET_STD_TSEC_INFO(tsec_info[num], 1);
  240. num++;
  241. #endif
  242. #ifdef CONFIG_TSEC2
  243. SET_STD_TSEC_INFO(tsec_info[num], 2);
  244. if (is_serdes_configured(SGMII_TSEC2)) {
  245. if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
  246. puts("eTSEC2 is in sgmii mode.\n");
  247. tsec_info[num].flags |= TSEC_SGMII;
  248. tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
  249. }
  250. }
  251. num++;
  252. #endif
  253. #ifdef CONFIG_TSEC3
  254. SET_STD_TSEC_INFO(tsec_info[num], 3);
  255. num++;
  256. #endif
  257. if (!num) {
  258. printf("No TSECs initialized\n");
  259. return 0;
  260. }
  261. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  262. mdio_info.name = DEFAULT_MII_NAME;
  263. fsl_pq_mdio_init(bis, &mdio_info);
  264. tsec_eth_init(bis, tsec_info, num);
  265. return pci_eth_init(bis);
  266. }
  267. #ifdef CONFIG_OF_BOARD_SETUP
  268. int ft_board_setup(void *blob, struct bd_info *bd)
  269. {
  270. phys_addr_t base;
  271. phys_size_t size;
  272. const char *soc_usb_compat = "fsl-usb2-dr";
  273. int err, usb1_off, usb2_off;
  274. ft_cpu_setup(blob, bd);
  275. base = env_get_bootm_low();
  276. size = env_get_bootm_size();
  277. fdt_fixup_memory(blob, (u64)base, (u64)size);
  278. FT_FSL_PCI_SETUP;
  279. #if defined(CONFIG_HAS_FSL_DR_USB)
  280. fsl_fdt_fixup_dr_usb(blob, bd);
  281. #endif
  282. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  283. /* Delete eLBC node as it is muxed with USB2 controller */
  284. if (hwconfig("usb2")) {
  285. const char *soc_elbc_compat = "fsl,p1020-elbc";
  286. int off = fdt_node_offset_by_compatible(blob, -1,
  287. soc_elbc_compat);
  288. if (off < 0) {
  289. printf
  290. ("WARNING: could not find compatible node %s: %s\n",
  291. soc_elbc_compat, fdt_strerror(off));
  292. return off;
  293. }
  294. err = fdt_del_node(blob, off);
  295. if (err < 0) {
  296. printf("WARNING: could not remove %s: %s\n",
  297. soc_elbc_compat, fdt_strerror(err));
  298. }
  299. return err;
  300. }
  301. #endif
  302. /* Delete USB2 node as it is muxed with eLBC */
  303. usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
  304. if (usb1_off < 0) {
  305. printf("WARNING: could not find compatible node %s: %s.\n",
  306. soc_usb_compat, fdt_strerror(usb1_off));
  307. return usb1_off;
  308. }
  309. usb2_off =
  310. fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
  311. if (usb2_off < 0) {
  312. printf("WARNING: could not find compatible node %s: %s.\n",
  313. soc_usb_compat, fdt_strerror(usb2_off));
  314. return usb2_off;
  315. }
  316. err = fdt_del_node(blob, usb2_off);
  317. if (err < 0) {
  318. printf("WARNING: could not remove %s: %s.\n",
  319. soc_usb_compat, fdt_strerror(err));
  320. }
  321. return 0;
  322. }
  323. #endif