spl.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013-2015 Arcturus Networks, Inc.
  4. * http://www.arcturusnetworks.com/products/ucp1020/
  5. * based on board/freescale/p1_p2_rdb_pc/spl.c
  6. * original copyright follows:
  7. * Copyright 2013 Freescale Semiconductor, Inc.
  8. */
  9. #include <common.h>
  10. #include <clock_legacy.h>
  11. #include <console.h>
  12. #include <env.h>
  13. #include <env_internal.h>
  14. #include <init.h>
  15. #include <ns16550.h>
  16. #include <malloc.h>
  17. #include <mmc.h>
  18. #include <nand.h>
  19. #include <i2c.h>
  20. #include <fsl_esdhc.h>
  21. #include <spi_flash.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. static const u32 sysclk_tbl[] = {
  24. 66666000, 7499900, 83332500, 8999900,
  25. 99999000, 11111000, 12499800, 13333200
  26. };
  27. phys_size_t get_effective_memsize(void)
  28. {
  29. return CONFIG_SYS_L2_SIZE;
  30. }
  31. void board_init_f(ulong bootflag)
  32. {
  33. u32 plat_ratio, bus_clk;
  34. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  35. console_init_f();
  36. /* Set pmuxcr to allow both i2c1 and i2c2 */
  37. setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
  38. setbits_be32(&gur->pmuxcr,
  39. in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
  40. /* Read back the register to synchronize the write. */
  41. in_be32(&gur->pmuxcr);
  42. #ifdef CONFIG_SPL_SPI_BOOT
  43. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  44. #endif
  45. /* initialize selected port with appropriate baud rate */
  46. plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  47. plat_ratio >>= 1;
  48. bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
  49. gd->bus_clk = bus_clk;
  50. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  51. bus_clk / 16 / CONFIG_BAUDRATE);
  52. #ifdef CONFIG_SPL_MMC_BOOT
  53. puts("\nSD boot...\n");
  54. #elif defined(CONFIG_SPL_SPI_BOOT)
  55. puts("\nSPI Flash boot...\n");
  56. #endif
  57. /* copy code to RAM and jump to it - this should not return */
  58. /* NOTE - code has to be copied out of NAND buffer before
  59. * other blocks can be read.
  60. */
  61. relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
  62. }
  63. void board_init_r(gd_t *gd, ulong dest_addr)
  64. {
  65. /* Pointer is writable since we allocated a register for it */
  66. gd = (gd_t *)CONFIG_SPL_GD_ADDR;
  67. struct bd_info *bd;
  68. memset(gd, 0, sizeof(gd_t));
  69. bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
  70. memset(bd, 0, sizeof(struct bd_info));
  71. gd->bd = bd;
  72. bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
  73. bd->bi_memsize = CONFIG_SYS_L2_SIZE;
  74. arch_cpu_init();
  75. get_clocks();
  76. mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  77. CONFIG_SPL_RELOC_MALLOC_SIZE);
  78. #ifndef CONFIG_SPL_NAND_BOOT
  79. env_init();
  80. #endif
  81. #ifdef CONFIG_SPL_MMC_BOOT
  82. mmc_initialize(bd);
  83. #endif
  84. /* relocate environment function pointers etc. */
  85. #ifdef CONFIG_SPL_NAND_BOOT
  86. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  87. (uchar *)CONFIG_ENV_ADDR);
  88. gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
  89. gd->env_valid = ENV_VALID;
  90. #else
  91. env_relocate();
  92. #endif
  93. #ifdef CONFIG_SYS_I2C
  94. i2c_init_all();
  95. #else
  96. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  97. #endif
  98. dram_init();
  99. #ifdef CONFIG_SPL_NAND_BOOT
  100. puts("Tertiary program loader running in sram...");
  101. #else
  102. puts("Second program loader running in sram...\n");
  103. #endif
  104. #ifdef CONFIG_SPL_MMC_BOOT
  105. mmc_boot();
  106. #elif defined(CONFIG_SPL_NAND_BOOT)
  107. nand_boot();
  108. #endif
  109. }