ddr.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013-2015 Arcturus Networks, Inc.
  4. * http://www.arcturusnetworks.com/products/ucp1020/
  5. * based on board/freescale/p1_p2_rdb_pc/spl.c
  6. * original copyright follows:
  7. * Copyright 2013 Freescale Semiconductor, Inc.
  8. */
  9. #include <common.h>
  10. #include <vsprintf.h>
  11. #include <asm/mmu.h>
  12. #include <asm/immap_85xx.h>
  13. #include <asm/processor.h>
  14. #include <fsl_ddr_sdram.h>
  15. #include <fsl_ddr_dimm_params.h>
  16. #include <asm/io.h>
  17. #include <asm/fsl_law.h>
  18. #ifdef CONFIG_SYS_DDR_RAW_TIMING
  19. #if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
  20. /*
  21. * Micron MT41J128M16HA-15E
  22. * */
  23. dimm_params_t ddr_raw_timing = {
  24. .n_ranks = 1,
  25. .rank_density = 536870912u,
  26. .capacity = 536870912u,
  27. .primary_sdram_width = 32,
  28. .ec_sdram_width = 8,
  29. .registered_dimm = 0,
  30. .mirrored_dimm = 0,
  31. .n_row_addr = 14,
  32. .n_col_addr = 10,
  33. .n_banks_per_sdram_device = 8,
  34. .edc_config = 2,
  35. .burst_lengths_bitmask = 0x0c,
  36. .tckmin_x_ps = 1650,
  37. .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
  38. .taa_ps = 14050,
  39. .twr_ps = 15000,
  40. .trcd_ps = 13500,
  41. .trrd_ps = 75000,
  42. .trp_ps = 13500,
  43. .tras_ps = 40000,
  44. .trc_ps = 49500,
  45. .trfc_ps = 160000,
  46. .twtr_ps = 75000,
  47. .trtp_ps = 75000,
  48. .refresh_rate_ps = 7800000,
  49. .tfaw_ps = 30000,
  50. };
  51. #else
  52. #error Missing raw timing data for this board
  53. #endif
  54. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  55. unsigned int controller_number,
  56. unsigned int dimm_number)
  57. {
  58. const char dimm_model[] = "Fixed DDR on board";
  59. if ((controller_number == 0) && (dimm_number == 0)) {
  60. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  61. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  62. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  63. }
  64. return 0;
  65. }
  66. #endif /* CONFIG_SYS_DDR_RAW_TIMING */
  67. #ifdef CONFIG_SYS_DDR_CS0_BNDS
  68. /* Fixed sdram init -- doesn't use serial presence detect. */
  69. phys_size_t fixed_sdram(void)
  70. {
  71. sys_info_t sysinfo;
  72. char buf[32];
  73. size_t ddr_size;
  74. fsl_ddr_cfg_regs_t ddr_cfg_regs = {
  75. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  76. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  77. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  78. #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
  79. .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  80. .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  81. .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
  82. #endif
  83. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
  84. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
  85. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
  86. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
  87. .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  88. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  89. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
  90. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
  91. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  92. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
  93. .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
  94. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
  95. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  96. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  97. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  98. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  99. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  100. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
  101. .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  102. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  103. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  104. };
  105. get_sys_info(&sysinfo);
  106. printf("Configuring DDR for %s MT/s data rate\n",
  107. strmhz(buf, sysinfo.freq_ddrbus));
  108. ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  109. fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  110. if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  111. ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
  112. printf("ERROR setting Local Access Windows for DDR\n");
  113. return 0;
  114. };
  115. return ddr_size;
  116. }
  117. #endif
  118. void fsl_ddr_board_options(memctl_options_t *popts,
  119. dimm_params_t *pdimm,
  120. unsigned int ctrl_num)
  121. {
  122. int i;
  123. popts->clk_adjust = 6;
  124. popts->cpo_override = 0x1f;
  125. popts->write_data_delay = 2;
  126. popts->half_strength_driver_enable = 1;
  127. /* Write leveling override */
  128. popts->wrlvl_en = 1;
  129. popts->wrlvl_override = 1;
  130. popts->wrlvl_sample = 0xf;
  131. popts->wrlvl_start = 0x8;
  132. popts->trwt_override = 1;
  133. popts->trwt = 0;
  134. if (pdimm->primary_sdram_width == 64)
  135. popts->data_bus_width = 0;
  136. else if (pdimm->primary_sdram_width == 32)
  137. popts->data_bus_width = 1;
  138. else
  139. printf("Error in DDR bus width configuration!\n");
  140. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  141. popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  142. popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  143. }
  144. }