tpl.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <debug_uart.h>
  7. #include <dm.h>
  8. #include <hang.h>
  9. #include <image.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <spl.h>
  13. #include <asm/cpu.h>
  14. #include <asm/mtrr.h>
  15. #include <asm/processor.h>
  16. #include <asm-generic/sections.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. __weak int arch_cpu_init_dm(void)
  19. {
  20. return 0;
  21. }
  22. static int x86_tpl_init(void)
  23. {
  24. int ret;
  25. debug("%s starting\n", __func__);
  26. ret = x86_cpu_init_tpl();
  27. if (ret) {
  28. debug("%s: x86_cpu_init_tpl() failed\n", __func__);
  29. return ret;
  30. }
  31. ret = spl_init();
  32. if (ret) {
  33. debug("%s: spl_init() failed\n", __func__);
  34. return ret;
  35. }
  36. ret = arch_cpu_init();
  37. if (ret) {
  38. debug("%s: arch_cpu_init() failed\n", __func__);
  39. return ret;
  40. }
  41. ret = arch_cpu_init_dm();
  42. if (ret) {
  43. debug("%s: arch_cpu_init_dm() failed\n", __func__);
  44. return ret;
  45. }
  46. preloader_console_init();
  47. return 0;
  48. }
  49. void board_init_f(ulong flags)
  50. {
  51. int ret;
  52. ret = x86_tpl_init();
  53. if (ret) {
  54. debug("Error %d\n", ret);
  55. panic("x86_tpl_init fail");
  56. }
  57. /* Uninit CAR and jump to board_init_f_r() */
  58. board_init_r(gd, 0);
  59. }
  60. void board_init_f_r(void)
  61. {
  62. /* Not used since we never call board_init_f_r_trampoline() */
  63. while (1);
  64. }
  65. u32 spl_boot_device(void)
  66. {
  67. return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT :
  68. BOOT_DEVICE_SPI_MMAP;
  69. }
  70. int spl_start_uboot(void)
  71. {
  72. return 0;
  73. }
  74. void spl_board_announce_boot_device(void)
  75. {
  76. printf("SPI flash");
  77. }
  78. static int spl_board_load_image(struct spl_image_info *spl_image,
  79. struct spl_boot_device *bootdev)
  80. {
  81. spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
  82. spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
  83. spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
  84. spl_image->os = IH_OS_U_BOOT;
  85. spl_image->name = "U-Boot";
  86. debug("Loading to %lx\n", spl_image->load_addr);
  87. return 0;
  88. }
  89. SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
  90. int spl_spi_load_image(void)
  91. {
  92. return -EPERM;
  93. }
  94. void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
  95. {
  96. debug("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point);
  97. jump_to_spl(spl_image->entry_point);
  98. hang();
  99. }
  100. void spl_board_init(void)
  101. {
  102. preloader_console_init();
  103. }
  104. #if !CONFIG_IS_ENABLED(PCI)
  105. /*
  106. * This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough
  107. * to bind the devices on the PCI bus, some of which have early-regs properties
  108. * providing fixed BARs. Individual drivers program these BARs themselves so
  109. * that they can access the devices. The BARs are allocated statically in the
  110. * device tree.
  111. *
  112. * Once SPL is running it enables PCI properly, but does not auto-assign BARs
  113. * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
  114. * the auto allocation (after relocation).
  115. */
  116. static const struct udevice_id tpl_fake_pci_ids[] = {
  117. { .compatible = "pci-x86" },
  118. { }
  119. };
  120. U_BOOT_DRIVER(pci_x86) = {
  121. .name = "pci_x86",
  122. .id = UCLASS_SIMPLE_BUS,
  123. .of_match = tpl_fake_pci_ids,
  124. };
  125. #endif