i8259.c 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Graeme Russ, <graeme.russ@gmail.com>
  5. *
  6. * (C) Copyright 2002
  7. * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  8. */
  9. /*
  10. * This file provides the interrupt handling functionality for systems
  11. * based on the standard PC/AT architecture using two cascaded i8259
  12. * Programmable Interrupt Controllers.
  13. */
  14. #include <common.h>
  15. #include <log.h>
  16. #include <asm/io.h>
  17. #include <asm/i8259.h>
  18. #include <asm/ibmpc.h>
  19. #include <asm/interrupt.h>
  20. int i8259_init(void)
  21. {
  22. u8 i;
  23. /* Mask all interrupts */
  24. outb(0xff, MASTER_PIC + IMR);
  25. outb(0xff, SLAVE_PIC + IMR);
  26. /*
  27. * Master PIC
  28. * Place master PIC interrupts at INT20
  29. */
  30. outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1);
  31. outb(0x20, MASTER_PIC + ICW2);
  32. outb(IR2, MASTER_PIC + ICW3);
  33. outb(ICW4_PM, MASTER_PIC + ICW4);
  34. for (i = 0; i < 8; i++)
  35. outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
  36. /*
  37. * Slave PIC
  38. * Place slave PIC interrupts at INT28
  39. */
  40. outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1);
  41. outb(0x28, SLAVE_PIC + ICW2);
  42. outb(0x02, SLAVE_PIC + ICW3);
  43. outb(ICW4_PM, SLAVE_PIC + ICW4);
  44. for (i = 0; i < 8; i++)
  45. outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);
  46. /*
  47. * Enable cascaded interrupts by unmasking the cascade IRQ pin of
  48. * the master PIC
  49. */
  50. unmask_irq(2);
  51. /* Interrupt 9 should be level triggered (SCI). The OS might do this */
  52. configure_irq_trigger(9, true);
  53. return 0;
  54. }
  55. void mask_irq(int irq)
  56. {
  57. int imr_port;
  58. if (irq >= SYS_NUM_IRQS)
  59. return;
  60. if (irq > 7)
  61. imr_port = SLAVE_PIC + IMR;
  62. else
  63. imr_port = MASTER_PIC + IMR;
  64. outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
  65. }
  66. void unmask_irq(int irq)
  67. {
  68. int imr_port;
  69. if (irq >= SYS_NUM_IRQS)
  70. return;
  71. if (irq > 7)
  72. imr_port = SLAVE_PIC + IMR;
  73. else
  74. imr_port = MASTER_PIC + IMR;
  75. outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
  76. }
  77. void specific_eoi(int irq)
  78. {
  79. if (irq >= SYS_NUM_IRQS)
  80. return;
  81. if (irq > 7) {
  82. /*
  83. * IRQ is on the slave - Issue a corresponding EOI to the
  84. * slave PIC and an EOI for IRQ2 (the cascade interrupt)
  85. * on the master PIC
  86. */
  87. outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
  88. irq = SEOI_IR2;
  89. }
  90. outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
  91. }
  92. void configure_irq_trigger(int int_num, bool is_level_triggered)
  93. {
  94. u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
  95. debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
  96. if (is_level_triggered)
  97. int_bits |= (1 << int_num);
  98. else
  99. int_bits &= ~(1 << int_num);
  100. /* Write new values */
  101. debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
  102. outb((u8)(int_bits & 0xff), ELCR1);
  103. outb((u8)(int_bits >> 8), ELCR2);
  104. }