coreboot_table.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <net.h>
  8. #include <vbe.h>
  9. #include <acpi/acpi_s3.h>
  10. #include <asm/coreboot_tables.h>
  11. #include <asm/e820.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. int high_table_reserve(void)
  14. {
  15. /* adjust stack pointer to reserve space for configuration tables */
  16. gd->arch.high_table_limit = gd->start_addr_sp;
  17. gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE;
  18. gd->arch.high_table_ptr = gd->start_addr_sp;
  19. /* clear the memory */
  20. if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
  21. gd->arch.prev_sleep_state != ACPI_S3) {
  22. memset((void *)gd->arch.high_table_ptr, 0,
  23. CONFIG_HIGH_TABLE_SIZE);
  24. }
  25. gd->start_addr_sp &= ~0xf;
  26. return 0;
  27. }
  28. void *high_table_malloc(size_t bytes)
  29. {
  30. u32 new_ptr;
  31. void *ptr;
  32. new_ptr = gd->arch.high_table_ptr + bytes;
  33. if (new_ptr >= gd->arch.high_table_limit)
  34. return NULL;
  35. ptr = (void *)gd->arch.high_table_ptr;
  36. gd->arch.high_table_ptr = new_ptr;
  37. return ptr;
  38. }
  39. /**
  40. * cb_table_init() - initialize a coreboot table header
  41. *
  42. * This fills in the coreboot table header signature and the header bytes.
  43. * Other fields are set to zero.
  44. *
  45. * @cbh: coreboot table header address
  46. */
  47. static void cb_table_init(struct cb_header *cbh)
  48. {
  49. memset(cbh, 0, sizeof(struct cb_header));
  50. memcpy(cbh->signature, "LBIO", 4);
  51. cbh->header_bytes = sizeof(struct cb_header);
  52. }
  53. /**
  54. * cb_table_add_entry() - add a coreboot table entry
  55. *
  56. * This increases the coreboot table entry size with added table entry length
  57. * and increases entry count by 1.
  58. *
  59. * @cbh: coreboot table header address
  60. * @cbr: to be added table entry address
  61. * @return: pointer to next table entry address
  62. */
  63. static u32 cb_table_add_entry(struct cb_header *cbh, struct cb_record *cbr)
  64. {
  65. cbh->table_bytes += cbr->size;
  66. cbh->table_entries++;
  67. return (u32)cbr + cbr->size;
  68. }
  69. /**
  70. * cb_table_finalize() - finalize the coreboot table
  71. *
  72. * This calculates the checksum for all coreboot table entries as well as
  73. * the checksum for the coreboot header itself.
  74. *
  75. * @cbh: coreboot table header address
  76. */
  77. static void cb_table_finalize(struct cb_header *cbh)
  78. {
  79. struct cb_record *cbr = (struct cb_record *)(cbh + 1);
  80. cbh->table_checksum = compute_ip_checksum(cbr, cbh->table_bytes);
  81. cbh->header_checksum = compute_ip_checksum(cbh, cbh->header_bytes);
  82. }
  83. void write_coreboot_table(u32 addr, struct memory_area *cfg_tables)
  84. {
  85. struct cb_header *cbh = (struct cb_header *)addr;
  86. struct cb_record *cbr;
  87. struct cb_memory *mem;
  88. struct cb_memory_range *map;
  89. struct e820_entry e820[32];
  90. struct cb_framebuffer *fb;
  91. struct vesa_mode_info *vesa;
  92. int i, num;
  93. cb_table_init(cbh);
  94. cbr = (struct cb_record *)(cbh + 1);
  95. /*
  96. * Two type of coreboot table entries are generated by us.
  97. * They are 'struct cb_memory' and 'struct cb_framebuffer'.
  98. */
  99. /* populate memory map table */
  100. mem = (struct cb_memory *)cbr;
  101. mem->tag = CB_TAG_MEMORY;
  102. map = mem->map;
  103. /* first install e820 defined memory maps */
  104. num = install_e820_map(ARRAY_SIZE(e820), e820);
  105. for (i = 0; i < num; i++) {
  106. map->start.lo = e820[i].addr & 0xffffffff;
  107. map->start.hi = e820[i].addr >> 32;
  108. map->size.lo = e820[i].size & 0xffffffff;
  109. map->size.hi = e820[i].size >> 32;
  110. map->type = e820[i].type;
  111. map++;
  112. }
  113. /* then install all configuration tables */
  114. while (cfg_tables->size) {
  115. map->start.lo = cfg_tables->start & 0xffffffff;
  116. map->start.hi = cfg_tables->start >> 32;
  117. map->size.lo = cfg_tables->size & 0xffffffff;
  118. map->size.hi = cfg_tables->size >> 32;
  119. map->type = CB_MEM_TABLE;
  120. map++;
  121. num++;
  122. cfg_tables++;
  123. }
  124. mem->size = num * sizeof(struct cb_memory_range) +
  125. sizeof(struct cb_record);
  126. cbr = (struct cb_record *)cb_table_add_entry(cbh, cbr);
  127. /* populate framebuffer table if we have sane vesa info */
  128. vesa = &mode_info.vesa;
  129. if (vesa->x_resolution && vesa->y_resolution) {
  130. fb = (struct cb_framebuffer *)cbr;
  131. fb->tag = CB_TAG_FRAMEBUFFER;
  132. fb->size = sizeof(struct cb_framebuffer);
  133. fb->x_resolution = vesa->x_resolution;
  134. fb->y_resolution = vesa->y_resolution;
  135. fb->bits_per_pixel = vesa->bits_per_pixel;
  136. fb->bytes_per_line = vesa->bytes_per_scanline;
  137. fb->physical_address = vesa->phys_base_ptr;
  138. fb->red_mask_size = vesa->red_mask_size;
  139. fb->red_mask_pos = vesa->red_mask_pos;
  140. fb->green_mask_size = vesa->green_mask_size;
  141. fb->green_mask_pos = vesa->green_mask_pos;
  142. fb->blue_mask_size = vesa->blue_mask_size;
  143. fb->blue_mask_pos = vesa->blue_mask_pos;
  144. fb->reserved_mask_size = vesa->reserved_mask_size;
  145. fb->reserved_mask_pos = vesa->reserved_mask_pos;
  146. cbr = (struct cb_record *)cb_table_add_entry(cbh, cbr);
  147. }
  148. cb_table_finalize(cbh);
  149. }