ppccache.S 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  4. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  5. * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
  6. * Copyright Freescale Semiconductor, Inc. 2004, 2006.
  7. */
  8. #include <config.h>
  9. #include <ppc_asm.tmpl>
  10. #include <ppc_defs.h>
  11. #include <asm/cache.h>
  12. /*------------------------------------------------------------------------------- */
  13. /* Function: ppcDcbf */
  14. /* Description: Data Cache block flush */
  15. /* Input: r3 = effective address */
  16. /* Output: none. */
  17. /*------------------------------------------------------------------------------- */
  18. .globl ppcDcbf
  19. ppcDcbf:
  20. dcbf r0,r3
  21. blr
  22. /*------------------------------------------------------------------------------- */
  23. /* Function: ppcDcbi */
  24. /* Description: Data Cache block Invalidate */
  25. /* Input: r3 = effective address */
  26. /* Output: none. */
  27. /*------------------------------------------------------------------------------- */
  28. .globl ppcDcbi
  29. ppcDcbi:
  30. dcbi r0,r3
  31. blr
  32. /*--------------------------------------------------------------------------
  33. * Function: ppcDcbz
  34. * Description: Data Cache block zero.
  35. * Input: r3 = effective address
  36. * Output: none.
  37. *-------------------------------------------------------------------------- */
  38. .globl ppcDcbz
  39. ppcDcbz:
  40. dcbz r0,r3
  41. blr
  42. /*------------------------------------------------------------------------------- */
  43. /* Function: ppcSync */
  44. /* Description: Processor Synchronize */
  45. /* Input: none. */
  46. /* Output: none. */
  47. /*------------------------------------------------------------------------------- */
  48. .globl ppcSync
  49. ppcSync:
  50. sync
  51. blr
  52. /*
  53. * Write any modified data cache blocks out to memory and invalidate them.
  54. * Does not invalidate the corresponding instruction cache blocks.
  55. *
  56. * flush_dcache_range(unsigned long start, unsigned long stop)
  57. */
  58. _GLOBAL(flush_dcache_range)
  59. #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
  60. li r5,L1_CACHE_BYTES-1
  61. andc r3,r3,r5
  62. subf r4,r3,r4
  63. add r4,r4,r5
  64. srwi. r4,r4,L1_CACHE_SHIFT
  65. beqlr
  66. mtctr r4
  67. 1: dcbf 0,r3
  68. addi r3,r3,L1_CACHE_BYTES
  69. bdnz 1b
  70. sync /* wait for dcbst's to get to ram */
  71. #endif
  72. blr
  73. /*
  74. * Like above, but invalidate the D-cache. This is used by the 8xx
  75. * to invalidate the cache so the PPC core doesn't get stale data
  76. * from the CPM (no cache snooping here :-).
  77. *
  78. * invalidate_dcache_range(unsigned long start, unsigned long stop)
  79. */
  80. _GLOBAL(invalidate_dcache_range)
  81. #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
  82. li r5,L1_CACHE_BYTES-1
  83. andc r3,r3,r5
  84. subf r4,r3,r4
  85. add r4,r4,r5
  86. srwi. r4,r4,L1_CACHE_SHIFT
  87. beqlr
  88. mtctr r4
  89. sync
  90. 1: dcbi 0,r3
  91. addi r3,r3,L1_CACHE_BYTES
  92. bdnz 1b
  93. sync /* wait for dcbi's to get to ram */
  94. #endif
  95. blr