srio.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <config.h>
  7. #include <log.h>
  8. #include <time.h>
  9. #include <asm/fsl_law.h>
  10. #include <asm/fsl_serdes.h>
  11. #include <asm/fsl_srio.h>
  12. #include <linux/delay.h>
  13. #include <linux/errno.h>
  14. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  15. #define SRIO_PORT_ACCEPT_ALL 0x10000001
  16. #define SRIO_IB_ATMU_AR 0x80f55000
  17. #define SRIO_OB_ATMU_AR_MAINT 0x80077000
  18. #define SRIO_OB_ATMU_AR_RW 0x80045000
  19. #define SRIO_LCSBA1CSR_OFFSET 0x5c
  20. #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
  21. #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
  22. #define SRIO_LCSBA1CSR 0x60000000
  23. #endif
  24. #if defined(CONFIG_FSL_CORENET)
  25. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  26. #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
  27. #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
  28. #else
  29. #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
  30. #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
  31. #endif
  32. #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
  33. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
  34. #elif defined(CONFIG_MPC85xx)
  35. #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
  36. #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
  37. #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
  38. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
  39. #elif defined(CONFIG_MPC86xx)
  40. #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
  41. #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
  42. #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
  43. #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
  44. (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
  45. #else
  46. #error "No defines for DEVDISR_SRIO"
  47. #endif
  48. #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  49. /*
  50. * Erratum A-004034
  51. * Affects: SRIO
  52. * Description: During port initialization, the SRIO port performs
  53. * lane synchronization (detecting valid symbols on a lane) and
  54. * lane alignment (coordinating multiple lanes to receive valid data
  55. * across lanes). Internal errors in lane synchronization and lane
  56. * alignment may cause failure to achieve link initialization at
  57. * the configured port width.
  58. * An SRIO port configured as a 4x port may see one of these scenarios:
  59. * 1. One or more lanes fails to achieve lane synchronization. Depending
  60. * on which lanes fail, this may result in downtraining from 4x to 1x
  61. * on lane 0, 4x to 1x on lane R (redundant lane).
  62. * 2. The link may fail to achieve lane alignment as a 4x, even though
  63. * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
  64. * An SRIO port configured as a 1x port may fail to complete port
  65. * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
  66. * Impact: SRIO port may downtrain to 1x, or may fail to complete
  67. * link initialization. Once a port completes link initialization
  68. * successfully, it will operate normally.
  69. */
  70. static int srio_erratum_a004034(u8 port)
  71. {
  72. serdes_corenet_t *srds_regs;
  73. u32 conf_lane;
  74. u32 init_lane;
  75. int idx, first, last;
  76. u32 i;
  77. unsigned long long end_tick;
  78. struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
  79. srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
  80. conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
  81. >> (12 - port * 4)) & 0x3;
  82. init_lane = (in_be32((void *)&srio_regs->lp_serial
  83. .port[port].pccsr) >> 27) & 0x7;
  84. /*
  85. * Start a counter set to ~2 ms after the SERDES reset is
  86. * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
  87. * corresponding to the SERDES bank/PLL for the SRIO port).
  88. */
  89. if (in_be32((void *)&srds_regs->bank[0].rstctl)
  90. & SRDS_RSTCTL_RSTDONE) {
  91. /*
  92. * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
  93. * PO=1 or the counter expires. If the counter expires, the
  94. * port has failed initialization: go to recover steps. If PO=1
  95. * and the desired port width is 1x, go to normal steps. If
  96. * PO = 1 and the desired port width is 4x, go to recover steps.
  97. */
  98. end_tick = usec2ticks(2000) + get_ticks();
  99. do {
  100. if (in_be32((void *)&srio_regs->lp_serial
  101. .port[port].pescsr) & 0x2) {
  102. if (conf_lane == 0x1)
  103. goto host_ok;
  104. else {
  105. if (init_lane == 0x2)
  106. goto host_ok;
  107. else
  108. break;
  109. }
  110. }
  111. } while (end_tick > get_ticks());
  112. /* recover at most 3 times */
  113. for (i = 0; i < 3; i++) {
  114. /* Set SRIO PnCCSR[PD]=1 */
  115. setbits_be32((void *)&srio_regs->lp_serial
  116. .port[port].pccsr,
  117. 0x800000);
  118. /*
  119. * Set SRIO PnPCR[OBDEN] on the host to
  120. * enable the discarding of any pending packets.
  121. */
  122. setbits_be32((void *)&srio_regs->impl.port[port].pcr,
  123. 0x04);
  124. /* Wait 50 us */
  125. udelay(50);
  126. /* Run sync command */
  127. isync();
  128. if (port)
  129. first = serdes_get_first_lane(SRIO2);
  130. else
  131. first = serdes_get_first_lane(SRIO1);
  132. if (unlikely(first < 0))
  133. return -ENODEV;
  134. if (conf_lane == 0x1)
  135. last = first;
  136. else
  137. last = first + 3;
  138. /*
  139. * Set SERDES BnGCRm0[RRST]=0 for each SRIO
  140. * bank n and lane m.
  141. */
  142. for (idx = first; idx <= last; idx++)
  143. clrbits_be32(&srds_regs->lane[idx].gcr0,
  144. SRDS_GCR0_RRST);
  145. /*
  146. * Read SERDES BnGCRm0 for each SRIO
  147. * bank n and lane m
  148. */
  149. for (idx = first; idx <= last; idx++)
  150. in_be32(&srds_regs->lane[idx].gcr0);
  151. /* Run sync command */
  152. isync();
  153. /* Wait >= 100 ns */
  154. udelay(1);
  155. /*
  156. * Set SERDES BnGCRm0[RRST]=1 for each SRIO
  157. * bank n and lane m.
  158. */
  159. for (idx = first; idx <= last; idx++)
  160. setbits_be32(&srds_regs->lane[idx].gcr0,
  161. SRDS_GCR0_RRST);
  162. /*
  163. * Read SERDES BnGCRm0 for each SRIO
  164. * bank n and lane m
  165. */
  166. for (idx = first; idx <= last; idx++)
  167. in_be32(&srds_regs->lane[idx].gcr0);
  168. /* Run sync command */
  169. isync();
  170. /* Wait >= 300 ns */
  171. udelay(1);
  172. /* Write 1 to clear all bits in SRIO PnSLCSR */
  173. out_be32((void *)&srio_regs->impl.port[port].slcsr,
  174. 0xffffffff);
  175. /* Clear SRIO PnPCR[OBDEN] on the host */
  176. clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
  177. 0x04);
  178. /* Set SRIO PnCCSR[PD]=0 */
  179. clrbits_be32((void *)&srio_regs->lp_serial
  180. .port[port].pccsr,
  181. 0x800000);
  182. /* Wait >= 24 ms */
  183. udelay(24000);
  184. /* Poll the state of the port again */
  185. init_lane =
  186. (in_be32((void *)&srio_regs->lp_serial
  187. .port[port].pccsr) >> 27) & 0x7;
  188. if (in_be32((void *)&srio_regs->lp_serial
  189. .port[port].pescsr) & 0x2) {
  190. if (conf_lane == 0x1)
  191. goto host_ok;
  192. else {
  193. if (init_lane == 0x2)
  194. goto host_ok;
  195. }
  196. }
  197. if (i == 2)
  198. return -ENODEV;
  199. }
  200. } else
  201. return -ENODEV;
  202. host_ok:
  203. /* Poll PnESCSR[OES] on the host until it is clear */
  204. end_tick = usec2ticks(1000000) + get_ticks();
  205. do {
  206. if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
  207. & 0x10000)) {
  208. out_be32(((void *)&srio_regs->lp_serial
  209. .port[port].pescsr), 0xffffffff);
  210. out_be32(((void *)&srio_regs->phys_err
  211. .port[port].edcsr), 0);
  212. out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
  213. return 0;
  214. }
  215. } while (end_tick > get_ticks());
  216. return -ENODEV;
  217. }
  218. #endif
  219. void srio_init(void)
  220. {
  221. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
  222. int srio1_used = 0, srio2_used = 0;
  223. u32 *devdisr;
  224. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  225. devdisr = &gur->devdisr3;
  226. #else
  227. devdisr = &gur->devdisr;
  228. #endif
  229. if (is_serdes_configured(SRIO1)) {
  230. set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
  231. law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
  232. LAW_TRGT_IF_RIO_1);
  233. srio1_used = 1;
  234. #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  235. if (srio_erratum_a004034(0) < 0)
  236. printf("SRIO1: enabled but port error\n");
  237. else
  238. #endif
  239. printf("SRIO1: enabled\n");
  240. } else {
  241. printf("SRIO1: disabled\n");
  242. }
  243. #ifdef CONFIG_SRIO2
  244. if (is_serdes_configured(SRIO2)) {
  245. set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
  246. law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
  247. LAW_TRGT_IF_RIO_2);
  248. srio2_used = 1;
  249. #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  250. if (srio_erratum_a004034(1) < 0)
  251. printf("SRIO2: enabled but port error\n");
  252. else
  253. #endif
  254. printf("SRIO2: enabled\n");
  255. } else {
  256. printf("SRIO2: disabled\n");
  257. }
  258. #endif
  259. #ifdef CONFIG_FSL_CORENET
  260. /* On FSL_CORENET devices we can disable individual ports */
  261. if (!srio1_used)
  262. setbits_be32(devdisr, _DEVDISR_SRIO1);
  263. if (!srio2_used)
  264. setbits_be32(devdisr, _DEVDISR_SRIO2);
  265. #endif
  266. /* neither port is used - disable everything */
  267. if (!srio1_used && !srio2_used) {
  268. setbits_be32(devdisr, _DEVDISR_SRIO1);
  269. setbits_be32(devdisr, _DEVDISR_SRIO2);
  270. setbits_be32(devdisr, _DEVDISR_RMU);
  271. }
  272. }
  273. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  274. void srio_boot_master(int port)
  275. {
  276. struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
  277. /* set port accept-all */
  278. out_be32((void *)&srio->impl.port[port - 1].ptaacr,
  279. SRIO_PORT_ACCEPT_ALL);
  280. debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
  281. /* configure inbound window for slave's u-boot image */
  282. debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
  283. "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
  284. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  285. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
  286. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  287. out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
  288. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
  289. out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
  290. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
  291. out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
  292. SRIO_IB_ATMU_AR
  293. | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
  294. /* configure inbound window for slave's u-boot image */
  295. debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
  296. "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
  297. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
  298. (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
  299. CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
  300. out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
  301. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
  302. out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
  303. CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
  304. out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
  305. SRIO_IB_ATMU_AR
  306. | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
  307. /* configure inbound window for slave's ucode and ENV */
  308. debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
  309. "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
  310. (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
  311. (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
  312. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
  313. out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
  314. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
  315. out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
  316. CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
  317. out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
  318. SRIO_IB_ATMU_AR
  319. | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
  320. }
  321. void srio_boot_master_release_slave(int port)
  322. {
  323. struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
  324. u32 escsr;
  325. debug("SRIOBOOT - MASTER: "
  326. "Check the port status and release slave core ...\n");
  327. escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr);
  328. if (escsr & 0x2) {
  329. if (escsr & 0x10100) {
  330. debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
  331. port);
  332. } else {
  333. debug("SRIOBOOT - MASTER: "
  334. "Port [ %d ] is ready, now release slave's core ...\n",
  335. port);
  336. /*
  337. * configure outbound window
  338. * with maintenance attribute to set slave's LCSBA1CSR
  339. */
  340. out_be32((void *)&srio->atmu.port[port - 1]
  341. .outbw[1].rowtar, 0);
  342. out_be32((void *)&srio->atmu.port[port - 1]
  343. .outbw[1].rowtear, 0);
  344. if (port - 1)
  345. out_be32((void *)&srio->atmu.port[port - 1]
  346. .outbw[1].rowbar,
  347. CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
  348. else
  349. out_be32((void *)&srio->atmu.port[port - 1]
  350. .outbw[1].rowbar,
  351. CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
  352. out_be32((void *)&srio->atmu.port[port - 1]
  353. .outbw[1].rowar,
  354. SRIO_OB_ATMU_AR_MAINT
  355. | atmu_size_mask(SRIO_MAINT_WIN_SIZE));
  356. /*
  357. * configure outbound window
  358. * with R/W attribute to set slave's BRR
  359. */
  360. out_be32((void *)&srio->atmu.port[port - 1]
  361. .outbw[2].rowtar,
  362. SRIO_LCSBA1CSR >> 9);
  363. out_be32((void *)&srio->atmu.port[port - 1]
  364. .outbw[2].rowtear, 0);
  365. if (port - 1)
  366. out_be32((void *)&srio->atmu.port[port - 1]
  367. .outbw[2].rowbar,
  368. (CONFIG_SYS_SRIO2_MEM_PHYS
  369. + SRIO_MAINT_WIN_SIZE) >> 12);
  370. else
  371. out_be32((void *)&srio->atmu.port[port - 1]
  372. .outbw[2].rowbar,
  373. (CONFIG_SYS_SRIO1_MEM_PHYS
  374. + SRIO_MAINT_WIN_SIZE) >> 12);
  375. out_be32((void *)&srio->atmu.port[port - 1]
  376. .outbw[2].rowar,
  377. SRIO_OB_ATMU_AR_RW
  378. | atmu_size_mask(SRIO_RW_WIN_SIZE));
  379. /*
  380. * Set the LCSBA1CSR register in slave
  381. * by the maint-outbound window
  382. */
  383. if (port - 1) {
  384. out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
  385. + SRIO_LCSBA1CSR_OFFSET,
  386. SRIO_LCSBA1CSR);
  387. while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
  388. + SRIO_LCSBA1CSR_OFFSET)
  389. != SRIO_LCSBA1CSR)
  390. ;
  391. /*
  392. * And then set the BRR register
  393. * to release slave core
  394. */
  395. out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
  396. + SRIO_MAINT_WIN_SIZE
  397. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
  398. CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
  399. } else {
  400. out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
  401. + SRIO_LCSBA1CSR_OFFSET,
  402. SRIO_LCSBA1CSR);
  403. while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
  404. + SRIO_LCSBA1CSR_OFFSET)
  405. != SRIO_LCSBA1CSR)
  406. ;
  407. /*
  408. * And then set the BRR register
  409. * to release slave core
  410. */
  411. out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
  412. + SRIO_MAINT_WIN_SIZE
  413. + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
  414. CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
  415. }
  416. debug("SRIOBOOT - MASTER: "
  417. "Release slave successfully! Now the slave should start up!\n");
  418. }
  419. } else
  420. debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port);
  421. }
  422. #endif