law.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2000
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #include <common.h>
  9. #include <asm/bitops.h>
  10. #include <linux/compiler.h>
  11. #include <asm/fsl_law.h>
  12. #include <asm/io.h>
  13. #include <linux/log2.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
  16. #ifdef CONFIG_FSL_CORENET
  17. #define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
  18. #define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
  19. #define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
  20. #define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
  21. #define LAWBAR_SHIFT 0
  22. #else
  23. #define LAW_BASE (CONFIG_SYS_IMMR + 0xc08)
  24. #define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2)
  25. #define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x)
  26. #define LAWBAR_SHIFT 12
  27. #endif
  28. static inline phys_addr_t get_law_base_addr(int idx)
  29. {
  30. #ifdef CONFIG_FSL_CORENET
  31. return (phys_addr_t)
  32. ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) |
  33. in_be32(LAWBARL_ADDR(idx));
  34. #else
  35. return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
  36. #endif
  37. }
  38. static inline void set_law_base_addr(int idx, phys_addr_t addr)
  39. {
  40. #ifdef CONFIG_FSL_CORENET
  41. out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff);
  42. out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32);
  43. #else
  44. out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
  45. #endif
  46. }
  47. void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
  48. {
  49. gd->arch.used_laws |= (1 << idx);
  50. out_be32(LAWAR_ADDR(idx), 0);
  51. set_law_base_addr(idx, addr);
  52. out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
  53. /* Read back so that we sync the writes */
  54. in_be32(LAWAR_ADDR(idx));
  55. }
  56. void disable_law(u8 idx)
  57. {
  58. gd->arch.used_laws &= ~(1 << idx);
  59. out_be32(LAWAR_ADDR(idx), 0);
  60. set_law_base_addr(idx, 0);
  61. /* Read back so that we sync the writes */
  62. in_be32(LAWAR_ADDR(idx));
  63. return;
  64. }
  65. #if !defined(CONFIG_NAND_SPL) && \
  66. (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
  67. static int get_law_entry(u8 i, struct law_entry *e)
  68. {
  69. u32 lawar;
  70. lawar = in_be32(LAWAR_ADDR(i));
  71. if (!(lawar & LAW_EN))
  72. return 0;
  73. e->addr = get_law_base_addr(i);
  74. e->size = lawar & 0x3f;
  75. e->trgt_id = (lawar >> 20) & 0xff;
  76. return 1;
  77. }
  78. #endif
  79. int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
  80. {
  81. u32 idx = ffz(gd->arch.used_laws);
  82. if (idx >= FSL_HW_NUM_LAWS)
  83. return -1;
  84. set_law(idx, addr, sz, id);
  85. return idx;
  86. }
  87. #if !defined(CONFIG_NAND_SPL) && \
  88. (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
  89. int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
  90. {
  91. u32 idx;
  92. /* we have no LAWs free */
  93. if (gd->arch.used_laws == -1)
  94. return -1;
  95. /* grab the last free law */
  96. idx = __ilog2(~(gd->arch.used_laws));
  97. if (idx >= FSL_HW_NUM_LAWS)
  98. return -1;
  99. set_law(idx, addr, sz, id);
  100. return idx;
  101. }
  102. struct law_entry find_law(phys_addr_t addr)
  103. {
  104. struct law_entry entry;
  105. int i;
  106. entry.index = -1;
  107. entry.addr = 0;
  108. entry.size = 0;
  109. entry.trgt_id = 0;
  110. for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
  111. u64 upper;
  112. if (!get_law_entry(i, &entry))
  113. continue;
  114. upper = entry.addr + (2ull << entry.size);
  115. if ((addr >= entry.addr) && (addr < upper)) {
  116. entry.index = i;
  117. break;
  118. }
  119. }
  120. return entry;
  121. }
  122. void print_laws(void)
  123. {
  124. int i;
  125. u32 lawar;
  126. printf("\nLocal Access Window Configuration\n");
  127. for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
  128. lawar = in_be32(LAWAR_ADDR(i));
  129. #ifdef CONFIG_FSL_CORENET
  130. printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
  131. i, in_be32(LAWBARH_ADDR(i)),
  132. i, in_be32(LAWBARL_ADDR(i)));
  133. #else
  134. printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
  135. #endif
  136. printf(" LAWAR%02d: 0x%08x\n", i, lawar);
  137. printf("\t(EN: %d TGT: 0x%02x SIZE: ",
  138. (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
  139. print_size(lawar_size(lawar), ")\n");
  140. }
  141. return;
  142. }
  143. /* use up to 2 LAWs for DDR, used the last available LAWs */
  144. int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
  145. {
  146. u64 start_align, law_sz;
  147. int law_sz_enc;
  148. if (start == 0)
  149. start_align = 1ull << (LAW_SIZE_32G + 1);
  150. else
  151. start_align = 1ull << (__ffs64(start));
  152. law_sz = min(start_align, sz);
  153. law_sz_enc = __ilog2_u64(law_sz) - 1;
  154. if (set_last_law(start, law_sz_enc, id) < 0)
  155. return -1;
  156. /* recalculate size based on what was actually covered by the law */
  157. law_sz = 1ull << __ilog2_u64(law_sz);
  158. /* do we still have anything to map */
  159. sz = sz - law_sz;
  160. if (sz) {
  161. start += law_sz;
  162. start_align = 1ull << (__ffs64(start));
  163. law_sz = min(start_align, sz);
  164. law_sz_enc = __ilog2_u64(law_sz) - 1;
  165. if (set_last_law(start, law_sz_enc, id) < 0)
  166. return -1;
  167. } else {
  168. return 0;
  169. }
  170. /* do we still have anything to map */
  171. sz = sz - law_sz;
  172. if (sz)
  173. return 1;
  174. return 0;
  175. }
  176. #endif /* not SPL */
  177. void disable_non_ddr_laws(void)
  178. {
  179. int i;
  180. int id;
  181. for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
  182. u32 lawar = in_be32(LAWAR_ADDR(i));
  183. if (lawar & LAW_EN) {
  184. id = (lawar & ~LAW_EN) >> 20;
  185. switch (id) {
  186. case LAW_TRGT_IF_DDR_1:
  187. case LAW_TRGT_IF_DDR_2:
  188. case LAW_TRGT_IF_DDR_3:
  189. case LAW_TRGT_IF_DDR_4:
  190. case LAW_TRGT_IF_DDR_INTRLV:
  191. case LAW_TRGT_IF_DDR_INTLV_34:
  192. case LAW_TRGT_IF_DDR_INTLV_123:
  193. case LAW_TRGT_IF_DDR_INTLV_1234:
  194. continue;
  195. default:
  196. disable_law(i);
  197. }
  198. }
  199. }
  200. }
  201. void init_laws(void)
  202. {
  203. int i;
  204. #if FSL_HW_NUM_LAWS < 32
  205. gd->arch.used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
  206. #elif FSL_HW_NUM_LAWS == 32
  207. gd->arch.used_laws = 0;
  208. #else
  209. #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
  210. #endif
  211. #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500) && \
  212. !defined(CONFIG_E500MC)
  213. /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms,
  214. * which is not disabled before transferring the control to uboot.
  215. * Disable the LAW 0 entry here.
  216. */
  217. disable_law(0);
  218. #endif
  219. #if !defined(CONFIG_NXP_ESBC)
  220. /*
  221. * if any non DDR LAWs has been created earlier, remove them before
  222. * LAW table is parsed.
  223. */
  224. disable_non_ddr_laws();
  225. #endif
  226. /*
  227. * Any LAWs that were set up before we booted assume they are meant to
  228. * be around and mark them used.
  229. */
  230. for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
  231. u32 lawar = in_be32(LAWAR_ADDR(i));
  232. if (lawar & LAW_EN)
  233. gd->arch.used_laws |= (1 << i);
  234. }
  235. for (i = 0; i < num_law_entries; i++) {
  236. if (law_table[i].index == -1)
  237. set_next_law(law_table[i].addr, law_table[i].size,
  238. law_table[i].trgt_id);
  239. else
  240. set_law(law_table[i].index, law_table[i].addr,
  241. law_table[i].size, law_table[i].trgt_id);
  242. }
  243. #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  244. /* check RCW to get which port is used for boot */
  245. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  246. u32 bootloc = in_be32(&gur->rcwsr[6]);
  247. /*
  248. * in SRIO or PCIE boot we need to set specail LAWs for
  249. * SRIO or PCIE interfaces.
  250. */
  251. switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
  252. case 0x0: /* boot from PCIE1 */
  253. set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  254. LAW_SIZE_1M,
  255. LAW_TRGT_IF_PCIE_1);
  256. set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
  257. LAW_SIZE_1M,
  258. LAW_TRGT_IF_PCIE_1);
  259. break;
  260. case 0x1: /* boot from PCIE2 */
  261. set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  262. LAW_SIZE_1M,
  263. LAW_TRGT_IF_PCIE_2);
  264. set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
  265. LAW_SIZE_1M,
  266. LAW_TRGT_IF_PCIE_2);
  267. break;
  268. case 0x2: /* boot from PCIE3 */
  269. set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  270. LAW_SIZE_1M,
  271. LAW_TRGT_IF_PCIE_3);
  272. set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
  273. LAW_SIZE_1M,
  274. LAW_TRGT_IF_PCIE_3);
  275. break;
  276. case 0x8: /* boot from SRIO1 */
  277. set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  278. LAW_SIZE_1M,
  279. LAW_TRGT_IF_RIO_1);
  280. set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
  281. LAW_SIZE_1M,
  282. LAW_TRGT_IF_RIO_1);
  283. break;
  284. case 0x9: /* boot from SRIO2 */
  285. set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  286. LAW_SIZE_1M,
  287. LAW_TRGT_IF_RIO_2);
  288. set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
  289. LAW_SIZE_1M,
  290. LAW_TRGT_IF_RIO_2);
  291. break;
  292. default:
  293. break;
  294. }
  295. #endif
  296. return ;
  297. }