cpu.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. *
  5. * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
  6. * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
  7. * cpu specific common code for 85xx/86xx processors.
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <command.h>
  12. #include <cpu_func.h>
  13. #include <init.h>
  14. #include <net.h>
  15. #include <tsec.h>
  16. #include <fm_eth.h>
  17. #include <netdev.h>
  18. #include <asm/cache.h>
  19. #include <asm/io.h>
  20. #include <vsc9953.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. static struct cpu_type cpu_type_list[] = {
  23. #if defined(CONFIG_MPC85xx)
  24. CPU_TYPE_ENTRY(8533, 8533, 1),
  25. CPU_TYPE_ENTRY(8535, 8535, 1),
  26. CPU_TYPE_ENTRY(8536, 8536, 1),
  27. CPU_TYPE_ENTRY(8540, 8540, 1),
  28. CPU_TYPE_ENTRY(8541, 8541, 1),
  29. CPU_TYPE_ENTRY(8543, 8543, 1),
  30. CPU_TYPE_ENTRY(8544, 8544, 1),
  31. CPU_TYPE_ENTRY(8545, 8545, 1),
  32. CPU_TYPE_ENTRY(8547, 8547, 1),
  33. CPU_TYPE_ENTRY(8548, 8548, 1),
  34. CPU_TYPE_ENTRY(8555, 8555, 1),
  35. CPU_TYPE_ENTRY(8560, 8560, 1),
  36. CPU_TYPE_ENTRY(8567, 8567, 1),
  37. CPU_TYPE_ENTRY(8568, 8568, 1),
  38. CPU_TYPE_ENTRY(8569, 8569, 1),
  39. CPU_TYPE_ENTRY(8572, 8572, 2),
  40. CPU_TYPE_ENTRY(P1010, P1010, 1),
  41. CPU_TYPE_ENTRY(P1011, P1011, 1),
  42. CPU_TYPE_ENTRY(P1012, P1012, 1),
  43. CPU_TYPE_ENTRY(P1013, P1013, 1),
  44. CPU_TYPE_ENTRY(P1014, P1014, 1),
  45. CPU_TYPE_ENTRY(P1017, P1017, 1),
  46. CPU_TYPE_ENTRY(P1020, P1020, 2),
  47. CPU_TYPE_ENTRY(P1021, P1021, 2),
  48. CPU_TYPE_ENTRY(P1022, P1022, 2),
  49. CPU_TYPE_ENTRY(P1023, P1023, 2),
  50. CPU_TYPE_ENTRY(P1024, P1024, 2),
  51. CPU_TYPE_ENTRY(P1025, P1025, 2),
  52. CPU_TYPE_ENTRY(P2010, P2010, 1),
  53. CPU_TYPE_ENTRY(P2020, P2020, 2),
  54. CPU_TYPE_ENTRY(P2040, P2040, 4),
  55. CPU_TYPE_ENTRY(P2041, P2041, 4),
  56. CPU_TYPE_ENTRY(P3041, P3041, 4),
  57. CPU_TYPE_ENTRY(P4040, P4040, 4),
  58. CPU_TYPE_ENTRY(P4080, P4080, 8),
  59. CPU_TYPE_ENTRY(P5010, P5010, 1),
  60. CPU_TYPE_ENTRY(P5020, P5020, 2),
  61. CPU_TYPE_ENTRY(P5021, P5021, 2),
  62. CPU_TYPE_ENTRY(P5040, P5040, 4),
  63. CPU_TYPE_ENTRY(T4240, T4240, 0),
  64. CPU_TYPE_ENTRY(T4120, T4120, 0),
  65. CPU_TYPE_ENTRY(T4160, T4160, 0),
  66. CPU_TYPE_ENTRY(T4080, T4080, 4),
  67. CPU_TYPE_ENTRY(B4860, B4860, 0),
  68. CPU_TYPE_ENTRY(G4860, G4860, 0),
  69. CPU_TYPE_ENTRY(B4440, B4440, 0),
  70. CPU_TYPE_ENTRY(B4460, B4460, 0),
  71. CPU_TYPE_ENTRY(G4440, G4440, 0),
  72. CPU_TYPE_ENTRY(B4420, B4420, 0),
  73. CPU_TYPE_ENTRY(B4220, B4220, 0),
  74. CPU_TYPE_ENTRY(T1040, T1040, 0),
  75. CPU_TYPE_ENTRY(T1041, T1041, 0),
  76. CPU_TYPE_ENTRY(T1042, T1042, 0),
  77. CPU_TYPE_ENTRY(T1020, T1020, 0),
  78. CPU_TYPE_ENTRY(T1021, T1021, 0),
  79. CPU_TYPE_ENTRY(T1022, T1022, 0),
  80. CPU_TYPE_ENTRY(T1024, T1024, 0),
  81. CPU_TYPE_ENTRY(T1023, T1023, 0),
  82. CPU_TYPE_ENTRY(T1014, T1014, 0),
  83. CPU_TYPE_ENTRY(T1013, T1013, 0),
  84. CPU_TYPE_ENTRY(T2080, T2080, 0),
  85. CPU_TYPE_ENTRY(T2081, T2081, 0),
  86. CPU_TYPE_ENTRY(BSC9130, 9130, 1),
  87. CPU_TYPE_ENTRY(BSC9131, 9131, 1),
  88. CPU_TYPE_ENTRY(BSC9132, 9132, 2),
  89. CPU_TYPE_ENTRY(BSC9232, 9232, 2),
  90. CPU_TYPE_ENTRY(C291, C291, 1),
  91. CPU_TYPE_ENTRY(C292, C292, 1),
  92. CPU_TYPE_ENTRY(C293, C293, 1),
  93. #elif defined(CONFIG_MPC86xx)
  94. CPU_TYPE_ENTRY(8610, 8610, 1),
  95. CPU_TYPE_ENTRY(8641, 8641, 2),
  96. CPU_TYPE_ENTRY(8641D, 8641D, 2),
  97. #endif
  98. };
  99. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  100. static inline u32 init_type(u32 cluster, int init_id)
  101. {
  102. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  103. u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
  104. u32 type = in_be32(&gur->tp_ityp[idx]);
  105. if (type & TP_ITYP_AV)
  106. return type;
  107. return 0;
  108. }
  109. u32 compute_ppc_cpumask(void)
  110. {
  111. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  112. int i = 0, count = 0;
  113. u32 cluster, type, mask = 0;
  114. do {
  115. int j;
  116. cluster = in_be32(&gur->tp_cluster[i].lower);
  117. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  118. type = init_type(cluster, j);
  119. if (type) {
  120. if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
  121. mask |= 1 << count;
  122. count++;
  123. }
  124. }
  125. i++;
  126. } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
  127. return mask;
  128. }
  129. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  130. u32 compute_dsp_cpumask(void)
  131. {
  132. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  133. int i = CONFIG_DSP_CLUSTER_START, count = 0;
  134. u32 cluster, type, dsp_mask = 0;
  135. do {
  136. int j;
  137. cluster = in_be32(&gur->tp_cluster[i].lower);
  138. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  139. type = init_type(cluster, j);
  140. if (type) {
  141. if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_SC)
  142. dsp_mask |= 1 << count;
  143. count++;
  144. }
  145. }
  146. i++;
  147. } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
  148. return dsp_mask;
  149. }
  150. int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
  151. {
  152. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  153. int count = 0, i = CONFIG_DSP_CLUSTER_START;
  154. u32 cluster;
  155. do {
  156. int j;
  157. cluster = in_be32(&gur->tp_cluster[i].lower);
  158. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  159. if (init_type(cluster, j)) {
  160. if (count == core)
  161. return i;
  162. count++;
  163. }
  164. }
  165. i++;
  166. } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
  167. return -1; /* cannot identify the cluster */
  168. }
  169. #endif
  170. int fsl_qoriq_core_to_cluster(unsigned int core)
  171. {
  172. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  173. int i = 0, count = 0;
  174. u32 cluster;
  175. do {
  176. int j;
  177. cluster = in_be32(&gur->tp_cluster[i].lower);
  178. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  179. if (init_type(cluster, j)) {
  180. if (count == core)
  181. return i;
  182. count++;
  183. }
  184. }
  185. i++;
  186. } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
  187. return -1; /* cannot identify the cluster */
  188. }
  189. #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  190. /*
  191. * Before chassis genenration 2, the cpumask should be hard-coded.
  192. * In case of cpu type unknown or cpumask unset, use 1 as fail save.
  193. */
  194. #define compute_ppc_cpumask() 1
  195. #define fsl_qoriq_core_to_cluster(x) x
  196. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  197. static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
  198. struct cpu_type *identify_cpu(u32 ver)
  199. {
  200. int i;
  201. for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) {
  202. if (cpu_type_list[i].soc_ver == ver)
  203. return &cpu_type_list[i];
  204. }
  205. return &cpu_type_unknown;
  206. }
  207. #define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
  208. #define MPC8xxx_PICFRR_NCPU_SHIFT 8
  209. /*
  210. * Return a 32-bit mask indicating which cores are present on this SOC.
  211. */
  212. __weak u32 cpu_mask(void)
  213. {
  214. ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
  215. struct cpu_type *cpu = gd->arch.cpu;
  216. /* better to query feature reporting register than just assume 1 */
  217. if (cpu == &cpu_type_unknown)
  218. return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
  219. MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
  220. if (cpu->num_cores == 0)
  221. return compute_ppc_cpumask();
  222. return cpu->mask;
  223. }
  224. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  225. __weak u32 cpu_dsp_mask(void)
  226. {
  227. ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
  228. struct cpu_type *cpu = gd->arch.cpu;
  229. /* better to query feature reporting register than just assume 1 */
  230. if (cpu == &cpu_type_unknown)
  231. return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
  232. MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
  233. if (cpu->dsp_num_cores == 0)
  234. return compute_dsp_cpumask();
  235. return cpu->dsp_mask;
  236. }
  237. /*
  238. * Return the number of SC/DSP cores on this SOC.
  239. */
  240. __weak int cpu_num_dspcores(void)
  241. {
  242. struct cpu_type *cpu = gd->arch.cpu;
  243. /*
  244. * Report # of cores in terms of the cpu_mask if we haven't
  245. * figured out how many there are yet
  246. */
  247. if (cpu->dsp_num_cores == 0)
  248. return hweight32(cpu_dsp_mask());
  249. return cpu->dsp_num_cores;
  250. }
  251. #endif
  252. /*
  253. * Return the number of PPC cores on this SOC.
  254. */
  255. __weak int cpu_numcores(void)
  256. {
  257. struct cpu_type *cpu = gd->arch.cpu;
  258. /*
  259. * Report # of cores in terms of the cpu_mask if we haven't
  260. * figured out how many there are yet
  261. */
  262. if (cpu->num_cores == 0)
  263. return hweight32(cpu_mask());
  264. return cpu->num_cores;
  265. }
  266. /*
  267. * Check if the given core ID is valid
  268. *
  269. * Returns zero if it isn't, 1 if it is.
  270. */
  271. int is_core_valid(unsigned int core)
  272. {
  273. return !!((1 << core) & cpu_mask());
  274. }
  275. int arch_cpu_init(void)
  276. {
  277. uint svr;
  278. uint ver;
  279. svr = get_svr();
  280. ver = SVR_SOC_VER(svr);
  281. gd->arch.cpu = identify_cpu(ver);
  282. return 0;
  283. }
  284. /* Once in memory, compute mask & # cores once and save them off */
  285. int fixup_cpu(void)
  286. {
  287. struct cpu_type *cpu = gd->arch.cpu;
  288. if (cpu->num_cores == 0) {
  289. cpu->mask = cpu_mask();
  290. cpu->num_cores = cpu_numcores();
  291. }
  292. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  293. if (cpu->dsp_num_cores == 0) {
  294. cpu->dsp_mask = cpu_dsp_mask();
  295. cpu->dsp_num_cores = cpu_num_dspcores();
  296. }
  297. #endif
  298. return 0;
  299. }
  300. /*
  301. * Initializes on-chip ethernet controllers.
  302. * to override, implement board_eth_init()
  303. */
  304. int cpu_eth_init(struct bd_info *bis)
  305. {
  306. #if defined(CONFIG_ETHER_ON_FCC)
  307. fec_initialize(bis);
  308. #endif
  309. #if defined(CONFIG_UEC_ETH)
  310. uec_standard_init(bis);
  311. #endif
  312. #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
  313. tsec_standard_init(bis);
  314. #endif
  315. #ifdef CONFIG_FMAN_ENET
  316. fm_standard_init(bis);
  317. #endif
  318. #ifdef CONFIG_VSC9953
  319. vsc9953_init(bis);
  320. #endif
  321. return 0;
  322. }