cpu.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /*
  7. * m8xx.c
  8. *
  9. * CPU specific code
  10. *
  11. * written or collected and sometimes rewritten by
  12. * Magnus Damm <damm@bitsmart.com>
  13. *
  14. * minor modifications by
  15. * Wolfgang Denk <wd@denx.de>
  16. */
  17. #include <common.h>
  18. #include <cpu_func.h>
  19. #include <net.h>
  20. #include <time.h>
  21. #include <vsprintf.h>
  22. #include <watchdog.h>
  23. #include <command.h>
  24. #include <mpc8xx.h>
  25. #include <netdev.h>
  26. #include <asm/cache.h>
  27. #include <asm/cpm_8xx.h>
  28. #include <linux/compiler.h>
  29. #include <asm/io.h>
  30. #if defined(CONFIG_OF_LIBFDT)
  31. #include <linux/libfdt.h>
  32. #include <fdt_support.h>
  33. #endif
  34. DECLARE_GLOBAL_DATA_PTR;
  35. /* ------------------------------------------------------------------------- */
  36. /* L1 i-cache */
  37. int checkicache(void)
  38. {
  39. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  40. memctl8xx_t __iomem *memctl = &immap->im_memctl;
  41. u32 cacheon = rd_ic_cst() & IDC_ENABLED;
  42. /* probe in flash memoryarea */
  43. u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
  44. u32 m;
  45. u32 lines = -1;
  46. wr_ic_cst(IDC_UNALL);
  47. wr_ic_cst(IDC_INVALL);
  48. wr_ic_cst(IDC_DISABLE);
  49. __asm__ volatile ("isync");
  50. while (!((m = rd_ic_cst()) & IDC_CERR2)) {
  51. wr_ic_adr(k);
  52. wr_ic_cst(IDC_LDLCK);
  53. __asm__ volatile ("isync");
  54. lines++;
  55. k += 0x10; /* the number of bytes in a cacheline */
  56. }
  57. wr_ic_cst(IDC_UNALL);
  58. wr_ic_cst(IDC_INVALL);
  59. if (cacheon)
  60. wr_ic_cst(IDC_ENABLE);
  61. else
  62. wr_ic_cst(IDC_DISABLE);
  63. __asm__ volatile ("isync");
  64. return lines << 4;
  65. };
  66. /* ------------------------------------------------------------------------- */
  67. /* L1 d-cache */
  68. /* call with cache disabled */
  69. static int checkdcache(void)
  70. {
  71. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  72. memctl8xx_t __iomem *memctl = &immap->im_memctl;
  73. u32 cacheon = rd_dc_cst() & IDC_ENABLED;
  74. /* probe in flash memoryarea */
  75. u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
  76. u32 m;
  77. u32 lines = -1;
  78. wr_dc_cst(IDC_UNALL);
  79. wr_dc_cst(IDC_INVALL);
  80. wr_dc_cst(IDC_DISABLE);
  81. while (!((m = rd_dc_cst()) & IDC_CERR2)) {
  82. wr_dc_adr(k);
  83. wr_dc_cst(IDC_LDLCK);
  84. lines++;
  85. k += 0x10; /* the number of bytes in a cacheline */
  86. }
  87. wr_dc_cst(IDC_UNALL);
  88. wr_dc_cst(IDC_INVALL);
  89. if (cacheon)
  90. wr_dc_cst(IDC_ENABLE);
  91. else
  92. wr_dc_cst(IDC_DISABLE);
  93. return lines << 4;
  94. };
  95. static int check_CPU(long clock, uint pvr, uint immr)
  96. {
  97. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  98. uint k;
  99. char buf[32];
  100. /* the highest 16 bits should be 0x0050 for a 860 */
  101. if (PVR_VER(pvr) != PVR_VER(PVR_8xx))
  102. return -1;
  103. k = (immr << 16) |
  104. in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
  105. /*
  106. * Some boards use sockets so different CPUs can be used.
  107. * We have to check chip version in run time.
  108. */
  109. switch (k) {
  110. /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
  111. case 0x08010004: /* Rev. A.0 */
  112. printf("MPC866xxxZPnnA");
  113. break;
  114. case 0x08000003: /* Rev. 0.3 */
  115. printf("MPC866xxxZPnn");
  116. break;
  117. case 0x09000000: /* 870/875/880/885 */
  118. puts("MPC885ZPnn");
  119. break;
  120. default:
  121. printf("unknown MPC86x (0x%08x)", k);
  122. break;
  123. }
  124. printf(" at %s MHz: ", strmhz(buf, clock));
  125. print_size(checkicache(), " I-Cache ");
  126. print_size(checkdcache(), " D-Cache");
  127. /* do we have a FEC (860T/P or 852/859/866/885)? */
  128. out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
  129. if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
  130. printf(" FEC present");
  131. putc('\n');
  132. return 0;
  133. }
  134. /* ------------------------------------------------------------------------- */
  135. int checkcpu(void)
  136. {
  137. ulong clock = gd->cpu_clk;
  138. uint immr = get_immr(); /* Return full IMMR contents */
  139. uint pvr = get_pvr();
  140. puts("CPU: ");
  141. return check_CPU(clock, pvr, immr);
  142. }
  143. /* ------------------------------------------------------------------------- */
  144. void upmconfig(uint upm, uint *table, uint size)
  145. {
  146. uint i;
  147. uint addr = 0;
  148. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  149. memctl8xx_t __iomem *memctl = &immap->im_memctl;
  150. for (i = 0; i < size; i++) {
  151. out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
  152. out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
  153. addr++;
  154. }
  155. }
  156. /* ------------------------------------------------------------------------- */
  157. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  158. {
  159. ulong msr, addr;
  160. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  161. /* Checkstop Reset enable */
  162. setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
  163. /* Interrupts and MMU off */
  164. __asm__ volatile ("mtspr 81, 0");
  165. __asm__ volatile ("mfmsr %0" : "=r" (msr));
  166. msr &= ~0x1030;
  167. __asm__ volatile ("mtmsr %0" : : "r" (msr));
  168. /*
  169. * Trying to execute the next instruction at a non-existing address
  170. * should cause a machine check, resulting in reset
  171. */
  172. #ifdef CONFIG_SYS_RESET_ADDRESS
  173. addr = CONFIG_SYS_RESET_ADDRESS;
  174. #else
  175. /*
  176. * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
  177. * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
  178. * Better pick an address known to be invalid on your system and assign
  179. * it to CONFIG_SYS_RESET_ADDRESS.
  180. * "(ulong)-1" used to be a good choice for many systems...
  181. */
  182. addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
  183. #endif
  184. ((void (*)(void)) addr)();
  185. return 1;
  186. }
  187. /* ------------------------------------------------------------------------- */
  188. /*
  189. * Get timebase clock frequency (like cpu_clk in Hz)
  190. *
  191. * See sections 14.2 and 14.6 of the User's Manual
  192. */
  193. unsigned long get_tbclk(void)
  194. {
  195. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  196. ulong oscclk, factor, pll;
  197. if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
  198. return gd->cpu_clk / 16;
  199. pll = in_be32(&immap->im_clkrst.car_plprcr);
  200. #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
  201. /*
  202. * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
  203. * factor is calculated as follows:
  204. *
  205. * MFN
  206. * MFI + -------
  207. * MFD + 1
  208. * factor = -----------------
  209. * (PDF + 1) * 2^S
  210. *
  211. */
  212. factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
  213. (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
  214. oscclk = gd->cpu_clk / factor;
  215. if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
  216. factor > 2)
  217. return oscclk / 4;
  218. return oscclk / 16;
  219. }
  220. /*
  221. * Initializes on-chip ethernet controllers.
  222. * to override, implement board_eth_init()
  223. */
  224. int cpu_eth_init(struct bd_info *bis)
  225. {
  226. #if defined(CONFIG_MPC8XX_FEC)
  227. fec_initialize(bis);
  228. #endif
  229. return 0;
  230. }