release.S 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2007, 2008 Freescale Semiconductor.
  4. * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
  5. */
  6. #include <config.h>
  7. #include <mpc86xx.h>
  8. #include <ppc_asm.tmpl>
  9. #include <ppc_defs.h>
  10. #include <asm/cache.h>
  11. #include <asm/mmu.h>
  12. /* If this is a multi-cpu system then we need to handle the
  13. * 2nd cpu. The assumption is that the 2nd cpu is being
  14. * held in boot holdoff mode until the 1st cpu unlocks it
  15. * from Linux. We'll do some basic cpu init and then pass
  16. * it to the Linux Reset Vector.
  17. * Sri: Much of this initialization is not required. Linux
  18. * rewrites the bats, and the sprs and also enables the L1 cache.
  19. *
  20. * Core 0 must copy this to a 1M aligned region and set BPTR
  21. * to point to it.
  22. */
  23. .align 12
  24. .globl __secondary_start_page
  25. __secondary_start_page:
  26. .space 0x100 /* space over to reset vector loc */
  27. mfspr r0, MSSCR0
  28. andi. r0, r0, 0x0020
  29. rlwinm r0,r0,27,31,31
  30. mtspr PIR, r0
  31. /* Invalidate BATs */
  32. li r0, 0
  33. mtspr IBAT0U, r0
  34. mtspr IBAT1U, r0
  35. mtspr IBAT2U, r0
  36. mtspr IBAT3U, r0
  37. mtspr IBAT4U, r0
  38. mtspr IBAT5U, r0
  39. mtspr IBAT6U, r0
  40. mtspr IBAT7U, r0
  41. isync
  42. mtspr DBAT0U, r0
  43. mtspr DBAT1U, r0
  44. mtspr DBAT2U, r0
  45. mtspr DBAT3U, r0
  46. mtspr DBAT4U, r0
  47. mtspr DBAT5U, r0
  48. mtspr DBAT6U, r0
  49. mtspr DBAT7U, r0
  50. isync
  51. sync
  52. /* enable extended addressing */
  53. mfspr r0, HID0
  54. lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
  55. ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
  56. mtspr HID0, r0
  57. sync
  58. isync
  59. #ifdef CONFIG_SYS_L2
  60. /* init the L2 cache */
  61. addis r3, r0, L2_INIT@h
  62. ori r3, r3, L2_INIT@l
  63. sync
  64. mtspr l2cr, r3
  65. #ifdef CONFIG_ALTIVEC
  66. dssall
  67. #endif
  68. /* invalidate the L2 cache */
  69. mfspr r3, l2cr
  70. rlwinm. r3, r3, 0, 0, 0
  71. beq 1f
  72. mfspr r3, l2cr
  73. rlwinm r3, r3, 0, 1, 31
  74. #ifdef CONFIG_ALTIVEC
  75. dssall
  76. #endif
  77. sync
  78. mtspr l2cr, r3
  79. sync
  80. 1: mfspr r3, l2cr
  81. oris r3, r3, L2CR_L2I@h
  82. mtspr l2cr, r3
  83. invl2:
  84. mfspr r3, l2cr
  85. andis. r3, r3, L2CR_L2I@h
  86. bne invl2
  87. sync
  88. #endif
  89. /* enable and invalidate the data cache */
  90. mfspr r3, HID0
  91. li r5, HID0_DCFI|HID0_DLOCK
  92. andc r3, r3, r5
  93. mtspr HID0, r3 /* no invalidate, unlock */
  94. ori r3, r3, HID0_DCE
  95. ori r5, r3, HID0_DCFI
  96. mtspr HID0, r5 /* enable + invalidate */
  97. mtspr HID0, r3 /* enable */
  98. sync
  99. #ifdef CONFIG_SYS_L2
  100. sync
  101. lis r3, L2_ENABLE@h
  102. ori r3, r3, L2_ENABLE@l
  103. mtspr l2cr, r3
  104. isync
  105. sync
  106. #endif
  107. /* enable and invalidate the instruction cache*/
  108. mfspr r3, HID0
  109. li r5, HID0_ICFI|HID0_ILOCK
  110. andc r3, r3, r5
  111. ori r3, r3, HID0_ICE
  112. ori r5, r3, HID0_ICFI
  113. mtspr HID0, r5
  114. mtspr HID0, r3
  115. isync
  116. sync
  117. /* TBEN in HID0 */
  118. mfspr r4, HID0
  119. oris r4, r4, 0x0400
  120. mtspr HID0, r4
  121. sync
  122. isync
  123. /* MCP|SYNCBE|ABE in HID1 */
  124. mfspr r4, HID1
  125. oris r4, r4, 0x8000
  126. ori r4, r4, 0x0C00
  127. mtspr HID1, r4
  128. sync
  129. isync
  130. lis r3, CONFIG_LINUX_RESET_VEC@h
  131. ori r3, r3, CONFIG_LINUX_RESET_VEC@l
  132. mtlr r3
  133. blr
  134. /* Never Returns, Running in Linux Now */