u-boot-spl.lds 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de
  5. *
  6. * Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include "config.h"
  9. OUTPUT_ARCH(powerpc)
  10. #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
  11. PHDRS
  12. {
  13. text PT_LOAD;
  14. bss PT_LOAD;
  15. }
  16. #endif
  17. SECTIONS
  18. {
  19. . = IMAGE_TEXT_BASE;
  20. .text : {
  21. *(.text*)
  22. }
  23. _etext = .;
  24. .reloc : {
  25. _GOT2_TABLE_ = .;
  26. KEEP(*(.got2))
  27. KEEP(*(.got))
  28. _FIXUP_TABLE_ = .;
  29. KEEP(*(.fixup))
  30. }
  31. __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
  32. __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
  33. . = ALIGN(8);
  34. .data : {
  35. *(.rodata*)
  36. *(.data*)
  37. *(.sdata*)
  38. }
  39. _edata = .;
  40. . = ALIGN(4);
  41. .u_boot_list : {
  42. KEEP(*(SORT(.u_boot_list*)));
  43. }
  44. . = .;
  45. __start___ex_table = .;
  46. __ex_table : { *(__ex_table) }
  47. __stop___ex_table = .;
  48. . = ALIGN(8);
  49. __init_begin = .;
  50. __init_end = .;
  51. _end = .;
  52. #ifdef CONFIG_SPL_SKIP_RELOCATE
  53. . = ALIGN(4);
  54. __bss_start = .;
  55. .bss : {
  56. *(.sbss*)
  57. *(.bss*)
  58. }
  59. . = ALIGN(4);
  60. __bss_end = .;
  61. #endif
  62. /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
  63. #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
  64. .bootpg ADDR(.text) - 0x1000 :
  65. {
  66. KEEP(*(.bootpg))
  67. } :text = 0xffff
  68. #else
  69. #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
  70. #ifndef BOOT_PAGE_OFFSET
  71. #define BOOT_PAGE_OFFSET 0x1000
  72. #endif
  73. .bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
  74. {
  75. arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
  76. }
  77. #ifndef RESET_VECTOR_OFFSET
  78. #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
  79. #endif
  80. #elif defined(CONFIG_FSL_ELBC)
  81. #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
  82. #else
  83. #error unknown NAND controller
  84. #endif
  85. .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
  86. KEEP(*(.resetvec))
  87. } = 0xffff
  88. #endif
  89. #ifndef CONFIG_SPL_SKIP_RELOCATE
  90. /*
  91. * Make sure that the bss segment isn't linked at 0x0, otherwise its
  92. * address won't be updated during relocation fixups.
  93. */
  94. . |= 0x10;
  95. . = ALIGN(4);
  96. __bss_start = .;
  97. .bss : {
  98. *(.sbss*)
  99. *(.bss*)
  100. }
  101. . = ALIGN(4);
  102. __bss_end = .;
  103. #endif
  104. }