t4240_serdes.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/fsl_serdes.h>
  7. #include <asm/processor.h>
  8. #include <asm/io.h>
  9. #include "fsl_corenet2_serdes.h"
  10. struct serdes_config {
  11. u32 protocol;
  12. u8 lanes[SRDS_MAX_LANES];
  13. };
  14. #ifdef CONFIG_ARCH_T4240
  15. static const struct serdes_config serdes1_cfg_tbl[] = {
  16. /* SerDes 1 */
  17. {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
  18. XAUI_FM1_MAC9, XAUI_FM1_MAC9,
  19. XAUI_FM1_MAC10, XAUI_FM1_MAC10,
  20. XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
  21. {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  22. HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  23. HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
  24. HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
  25. {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  26. HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  27. HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
  28. HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
  29. {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  30. SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
  31. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  32. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
  33. {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  34. SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
  35. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  36. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
  37. {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  38. SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
  39. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  40. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
  41. {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  42. SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
  43. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  44. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
  45. {37, {NONE, NONE, QSGMII_FM1_B, NONE,
  46. NONE, NONE, QSGMII_FM1_A, NONE} },
  47. {38, {NONE, NONE, QSGMII_FM1_B, NONE,
  48. NONE, NONE, QSGMII_FM1_A, NONE}},
  49. {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  50. SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
  51. NONE, NONE, QSGMII_FM1_A, NONE} },
  52. {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  53. SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
  54. NONE, NONE, QSGMII_FM1_A, NONE}},
  55. {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  56. SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
  57. NONE, NONE, QSGMII_FM1_A, NONE} },
  58. {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  59. SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
  60. NONE, NONE, QSGMII_FM1_A, NONE}},
  61. {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  62. SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
  63. NONE, NONE, QSGMII_FM1_A, NONE} },
  64. {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  65. SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
  66. NONE, NONE, QSGMII_FM1_A, NONE}},
  67. {}
  68. };
  69. static const struct serdes_config serdes2_cfg_tbl[] = {
  70. /* SerDes 2 */
  71. {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  72. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  73. XAUI_FM2_MAC10, XAUI_FM2_MAC10,
  74. XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
  75. {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  76. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  77. HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
  78. HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
  79. {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  80. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  81. HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
  82. HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
  83. {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  84. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  85. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  86. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  87. {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  88. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  89. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  90. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  91. {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  92. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  93. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  94. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  95. {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  96. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  97. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  98. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  99. {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  100. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  101. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  102. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  103. {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  104. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  105. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  106. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  107. {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  108. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  109. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  110. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  111. {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  112. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  113. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  114. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  115. {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  116. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  117. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  118. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  119. {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  120. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  121. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  122. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  123. {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  124. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  125. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  126. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  127. {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  128. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  129. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  130. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  131. {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  132. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  133. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  134. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  135. {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  136. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  137. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  138. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  139. {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  140. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  141. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  142. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  143. {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  144. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  145. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  146. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  147. {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  148. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  149. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  150. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  151. {37, {NONE, NONE, QSGMII_FM2_B, NONE,
  152. NONE, NONE, QSGMII_FM2_A, NONE} },
  153. {38, {NONE, NONE, QSGMII_FM2_B, NONE,
  154. NONE, NONE, QSGMII_FM2_A, NONE} },
  155. {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  156. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  157. NONE, NONE, QSGMII_FM2_A, NONE} },
  158. {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  159. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  160. NONE, NONE, QSGMII_FM2_A, NONE} },
  161. {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  162. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  163. NONE, NONE, QSGMII_FM2_A, NONE} },
  164. {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  165. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  166. NONE, NONE, QSGMII_FM2_A, NONE} },
  167. {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  168. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  169. NONE, NONE, QSGMII_FM2_A, NONE} },
  170. {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  171. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  172. NONE, NONE, QSGMII_FM2_A, NONE} },
  173. {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  174. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  175. NONE, NONE, QSGMII_FM2_A, NONE} },
  176. {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  177. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  178. NONE, NONE, QSGMII_FM2_A, NONE} },
  179. {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  180. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  181. NONE, NONE, QSGMII_FM2_A, NONE} },
  182. {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  183. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  184. NONE, NONE, QSGMII_FM2_A, NONE} },
  185. {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  186. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  187. NONE, NONE, QSGMII_FM2_A, NONE} },
  188. {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  189. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  190. NONE, NONE, QSGMII_FM2_A, NONE} },
  191. {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  192. XFI_FM2_MAC10, XFI_FM2_MAC9,
  193. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  194. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  195. {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  196. XFI_FM2_MAC10, XFI_FM2_MAC9,
  197. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  198. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  199. {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  200. XFI_FM2_MAC10, XFI_FM2_MAC9,
  201. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  202. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
  203. {}
  204. };
  205. static const struct serdes_config serdes3_cfg_tbl[] = {
  206. /* SerDes 3 */
  207. {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
  208. {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
  209. {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
  210. {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
  211. {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
  212. {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
  213. {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
  214. {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
  215. {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  216. INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
  217. {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  218. INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
  219. {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  220. PCIE2, PCIE2, PCIE2, PCIE2} },
  221. {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  222. PCIE2, PCIE2, PCIE2, PCIE2}},
  223. {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  224. PCIE2, PCIE2, PCIE2, PCIE2} },
  225. {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  226. PCIE2, PCIE2, PCIE2, PCIE2}},
  227. {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  228. SRIO1, SRIO1, SRIO1, SRIO1} },
  229. {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  230. SRIO1, SRIO1, SRIO1, SRIO1}},
  231. {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  232. SRIO1, SRIO1, SRIO1, SRIO1}},
  233. {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  234. SRIO1, SRIO1, SRIO1, SRIO1} },
  235. {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  236. SRIO1, SRIO1, SRIO1, SRIO1}},
  237. {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  238. SRIO1, SRIO1, SRIO1, SRIO1}},
  239. {}
  240. };
  241. static const struct serdes_config serdes4_cfg_tbl[] = {
  242. /* SerDes 4 */
  243. {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
  244. {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
  245. {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
  246. {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
  247. {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
  248. {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
  249. {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
  250. {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
  251. {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
  252. {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
  253. {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
  254. {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
  255. {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
  256. {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
  257. {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
  258. {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
  259. {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
  260. {}
  261. };
  262. #elif defined(CONFIG_ARCH_T4160)
  263. static const struct serdes_config serdes1_cfg_tbl[] = {
  264. /* SerDes 1 */
  265. {1, {NONE, NONE, NONE, NONE,
  266. XAUI_FM1_MAC10, XAUI_FM1_MAC10,
  267. XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
  268. {2, {NONE, NONE, NONE, NONE,
  269. HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
  270. HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
  271. {4, {NONE, NONE, NONE, NONE,
  272. HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
  273. HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
  274. {27, {NONE, NONE, NONE, NONE,
  275. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  276. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
  277. {28, {NONE, NONE, NONE, NONE,
  278. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  279. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
  280. {35, {NONE, NONE, NONE, NONE,
  281. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  282. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
  283. {36, {NONE, NONE, NONE, NONE,
  284. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  285. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
  286. {37, {NONE, NONE, NONE, NONE,
  287. NONE, NONE, QSGMII_FM1_A, NONE} },
  288. {38, {NONE, NONE, NONE, NONE,
  289. NONE, NONE, QSGMII_FM1_A, NONE} },
  290. {}
  291. };
  292. static const struct serdes_config serdes2_cfg_tbl[] = {
  293. /* SerDes 2 */
  294. {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  295. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  296. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  297. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  298. {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  299. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  300. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  301. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  302. {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  303. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  304. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  305. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  306. {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  307. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  308. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  309. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  310. {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  311. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  312. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  313. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  314. {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  315. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  316. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  317. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  318. {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  319. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  320. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  321. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  322. {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  323. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  324. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  325. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  326. {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  327. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  328. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  329. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  330. {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  331. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  332. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  333. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  334. {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  335. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  336. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  337. NONE, NONE} },
  338. {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  339. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  340. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  341. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  342. {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  343. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  344. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  345. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  346. {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  347. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  348. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  349. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  350. {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  351. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  352. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  353. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  354. {37, {NONE, NONE, QSGMII_FM2_B, NONE,
  355. NONE, NONE, QSGMII_FM2_A, NONE} },
  356. {38, {NONE, NONE, QSGMII_FM2_B, NONE,
  357. NONE, NONE, QSGMII_FM2_A, NONE} },
  358. {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  359. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  360. NONE, NONE, QSGMII_FM2_A, NONE} },
  361. {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  362. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  363. NONE, NONE, QSGMII_FM2_A, NONE} },
  364. {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  365. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  366. NONE, NONE, QSGMII_FM2_A, NONE} },
  367. {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  368. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  369. NONE, NONE, QSGMII_FM2_A, NONE} },
  370. {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  371. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  372. NONE, NONE, QSGMII_FM2_A, NONE} },
  373. {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
  374. SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
  375. NONE, NONE, QSGMII_FM2_A, NONE} },
  376. {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  377. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  378. NONE, NONE, QSGMII_FM2_A, NONE} },
  379. {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  380. XAUI_FM2_MAC9, XAUI_FM2_MAC9,
  381. NONE, NONE, QSGMII_FM2_A, NONE} },
  382. {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  383. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  384. NONE, NONE, QSGMII_FM2_A, NONE} },
  385. {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  386. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  387. NONE, NONE, QSGMII_FM2_A, NONE} },
  388. {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  389. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  390. NONE, NONE, QSGMII_FM2_A, NONE} },
  391. {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  392. HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
  393. NONE, NONE, QSGMII_FM2_A, NONE} },
  394. {55, {NONE, XFI_FM1_MAC10,
  395. XFI_FM2_MAC10, NONE,
  396. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  397. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  398. {56, {NONE, XFI_FM1_MAC10,
  399. XFI_FM2_MAC10, NONE,
  400. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  401. SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
  402. {57, {NONE, XFI_FM1_MAC10,
  403. XFI_FM2_MAC10, NONE,
  404. SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
  405. NONE, NONE} },
  406. {}
  407. };
  408. static const struct serdes_config serdes3_cfg_tbl[] = {
  409. /* SerDes 3 */
  410. {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
  411. {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
  412. {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
  413. {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
  414. {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
  415. {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
  416. {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
  417. {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
  418. {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  419. INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
  420. {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  421. INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
  422. {11, {NONE, NONE, NONE, NONE,
  423. PCIE2, PCIE2, PCIE2, PCIE2} },
  424. {12, {NONE, NONE, NONE, NONE,
  425. PCIE2, PCIE2, PCIE2, PCIE2} },
  426. {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  427. PCIE2, PCIE2, PCIE2, PCIE2} },
  428. {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  429. PCIE2, PCIE2, PCIE2, PCIE2} },
  430. {15, {NONE, NONE, NONE, NONE,
  431. SRIO1, SRIO1, SRIO1, SRIO1} },
  432. {16, {NONE, NONE, NONE, NONE,
  433. SRIO1, SRIO1, SRIO1, SRIO1} },
  434. {17, {NONE, NONE, NONE, NONE,
  435. SRIO1, SRIO1, SRIO1, SRIO1} },
  436. {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  437. SRIO1, SRIO1, SRIO1, SRIO1} },
  438. {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  439. SRIO1, SRIO1, SRIO1, SRIO1} },
  440. {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
  441. SRIO1, SRIO1, SRIO1, SRIO1} },
  442. {}
  443. };
  444. static const struct serdes_config serdes4_cfg_tbl[] = {
  445. /* SerDes 4 */
  446. {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
  447. {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
  448. {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
  449. {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
  450. {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
  451. {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
  452. {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
  453. {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
  454. {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
  455. {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
  456. {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
  457. {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
  458. {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
  459. {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
  460. {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
  461. {}
  462. }
  463. ;
  464. #else
  465. #error "Need to define SerDes protocol"
  466. #endif
  467. static const struct serdes_config *serdes_cfg_tbl[] = {
  468. serdes1_cfg_tbl,
  469. serdes2_cfg_tbl,
  470. serdes3_cfg_tbl,
  471. serdes4_cfg_tbl,
  472. };
  473. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  474. {
  475. const struct serdes_config *ptr;
  476. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  477. return 0;
  478. ptr = serdes_cfg_tbl[serdes];
  479. while (ptr->protocol) {
  480. if (ptr->protocol == cfg)
  481. return ptr->lanes[lane];
  482. ptr++;
  483. }
  484. return 0;
  485. }
  486. int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  487. {
  488. int i;
  489. const struct serdes_config *ptr;
  490. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  491. return 0;
  492. ptr = serdes_cfg_tbl[serdes];
  493. while (ptr->protocol) {
  494. if (ptr->protocol == prtcl)
  495. break;
  496. ptr++;
  497. }
  498. if (!ptr->protocol)
  499. return 0;
  500. for (i = 0; i < SRDS_MAX_LANES; i++) {
  501. if (ptr->lanes[i] != NONE)
  502. return 1;
  503. }
  504. return 0;
  505. }