t2080_serdes.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. *
  5. * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <asm/fsl_serdes.h>
  9. #include <asm/processor.h>
  10. #include "fsl_corenet2_serdes.h"
  11. struct serdes_config {
  12. u32 protocol;
  13. u8 lanes[SRDS_MAX_LANES];
  14. };
  15. static const struct serdes_config serdes1_cfg_tbl[] = {
  16. /* SerDes 1 */
  17. {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  18. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  19. PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  20. {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1,
  21. SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} },
  22. {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  23. SGMII_FM1_DTSEC2, PCIE4, PCIE4,
  24. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  25. {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  26. SGMII_FM1_DTSEC2, PCIE4, PCIE4,
  27. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  28. {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3,
  29. PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
  30. {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4,
  31. PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  32. {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  33. SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
  34. {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  35. SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
  36. {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  37. SGMII_FM1_DTSEC2, PCIE4, PCIE1,
  38. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  39. {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  40. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  41. PCIE4, PCIE4, PCIE4, PCIE4} },
  42. {0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  43. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  44. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  45. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  46. {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  47. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  48. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  49. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  50. {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  51. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  52. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  53. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  54. {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  55. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  56. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  57. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  58. {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  59. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  60. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  61. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  62. {0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
  63. XAUI_FM1_MAC9, XAUI_FM1_MAC9,
  64. PCIE4, SGMII_FM1_DTSEC4,
  65. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  66. {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
  67. XAUI_FM1_MAC9, XAUI_FM1_MAC9,
  68. PCIE4, SGMII_FM1_DTSEC4,
  69. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  70. {0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  71. HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  72. PCIE4, SGMII_FM1_DTSEC4,
  73. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  74. {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  75. HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  76. PCIE4, SGMII_FM1_DTSEC4,
  77. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  78. {0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  79. HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  80. PCIE4, SGMII_FM1_DTSEC4,
  81. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  82. {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  83. HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
  84. PCIE4, SGMII_FM1_DTSEC4,
  85. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  86. {0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  87. XFI_FM1_MAC1, XFI_FM1_MAC2,
  88. PCIE4, SGMII_FM1_DTSEC4,
  89. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  90. {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  91. XFI_FM1_MAC1, XFI_FM1_MAC2,
  92. PCIE4, SGMII_FM1_DTSEC4,
  93. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  94. {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  95. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  96. PCIE4, PCIE4, PCIE4, PCIE4} },
  97. {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  98. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
  99. SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  100. {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  101. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
  102. PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  103. {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  104. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
  105. PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  106. {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  107. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
  108. PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  109. {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  110. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  111. PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  112. {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  113. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  114. PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  115. {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  116. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  117. PCIE4, PCIE4, PCIE4, PCIE4} },
  118. {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  119. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  120. PCIE4, PCIE4, PCIE4, PCIE4} },
  121. {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
  122. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  123. PCIE4, PCIE4, PCIE4, PCIE4} },
  124. {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  125. XFI_FM1_MAC1, XFI_FM1_MAC2,
  126. PCIE4, PCIE4, PCIE4, PCIE4} },
  127. {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3,
  128. PCIE4, PCIE4, PCIE4, PCIE4} },
  129. {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3,
  130. PCIE3, PCIE3, PCIE3, PCIE3} },
  131. {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  132. SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
  133. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  134. {0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  135. SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
  136. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  137. {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  138. SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
  139. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  140. {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  141. SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
  142. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  143. {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  144. SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
  145. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  146. {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
  147. XFI_FM1_MAC1, XFI_FM1_MAC2,
  148. PCIE4, PCIE4, PCIE4, PCIE4} },
  149. {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
  150. PCIE4, PCIE4, PCIE4, PCIE4} },
  151. {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
  152. SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
  153. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  154. {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
  155. SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
  156. SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  157. {}
  158. };
  159. #ifndef CONFIG_ARCH_T2081
  160. static const struct serdes_config serdes2_cfg_tbl[] = {
  161. /* SerDes 2 */
  162. {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
  163. {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
  164. {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
  165. {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
  166. {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
  167. {0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
  168. {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
  169. {0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} },
  170. {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
  171. {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
  172. {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
  173. {}
  174. };
  175. #endif
  176. static const struct serdes_config *serdes_cfg_tbl[] = {
  177. serdes1_cfg_tbl,
  178. #ifndef CONFIG_ARCH_T2081
  179. serdes2_cfg_tbl,
  180. #endif
  181. };
  182. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  183. {
  184. const struct serdes_config *ptr;
  185. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  186. return 0;
  187. ptr = serdes_cfg_tbl[serdes];
  188. while (ptr->protocol) {
  189. if (ptr->protocol == cfg)
  190. return ptr->lanes[lane];
  191. ptr++;
  192. }
  193. return 0;
  194. }
  195. int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  196. {
  197. int i;
  198. const struct serdes_config *ptr;
  199. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  200. return 0;
  201. ptr = serdes_cfg_tbl[serdes];
  202. while (ptr->protocol) {
  203. if (ptr->protocol == prtcl)
  204. break;
  205. ptr++;
  206. }
  207. if (!ptr->protocol)
  208. return 0;
  209. for (i = 0; i < SRDS_MAX_LANES; i++) {
  210. if (ptr->lanes[i] != NONE)
  211. return 1;
  212. }
  213. return 0;
  214. }