t1040_serdes.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/fsl_serdes.h>
  7. #include <asm/processor.h>
  8. #include <asm/io.h>
  9. static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
  10. [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
  11. PCIE2, PCIE2, PCIE2, PCIE2},
  12. [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
  13. PCIE2, PCIE3, PCIE4, SATA1},
  14. [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
  15. PCIE2, PCIE3, SATA2, SATA1},
  16. [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  17. PCIE2, PCIE2, PCIE2, PCIE2},
  18. [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
  19. PCIE2, PCIE2, PCIE2, PCIE2},
  20. [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
  21. PCIE2, PCIE3, PCIE4, SATA1},
  22. [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
  23. PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
  24. [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
  25. PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
  26. [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  27. PCIE2, PCIE3, PCIE4, SATA1},
  28. [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  29. PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
  30. [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  31. PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
  32. [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
  33. PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
  34. [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
  35. PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
  36. [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  37. AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
  38. [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  39. PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
  40. [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  41. PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
  42. [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  43. PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
  44. };
  45. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  46. {
  47. return serdes_cfg_tbl[cfg][lane];
  48. }
  49. int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  50. {
  51. int i;
  52. if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
  53. return 0;
  54. for (i = 0; i < SRDS_MAX_LANES; i++) {
  55. if (serdes_cfg_tbl[prtcl][i] != NONE)
  56. return 1;
  57. }
  58. return 0;
  59. }