t1024_serdes.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/fsl_serdes.h>
  7. #include <asm/processor.h>
  8. #include <asm/io.h>
  9. static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
  10. [0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
  11. [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
  12. [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
  13. [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
  14. [0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
  15. [0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
  16. [0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
  17. [0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
  18. [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
  19. [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
  20. [0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
  21. [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
  22. [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
  23. [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
  24. SGMII_2500_FM1_DTSEC1},
  25. [0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
  26. [0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
  27. SGMII_2500_FM1_DTSEC1},
  28. [0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
  29. [0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
  30. };
  31. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  32. {
  33. return serdes_cfg_tbl[cfg][lane];
  34. }
  35. int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  36. {
  37. int i;
  38. if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
  39. return 0;
  40. for (i = 0; i < SRDS_MAX_LANES; i++) {
  41. if (serdes_cfg_tbl[prtcl][i] != NONE)
  42. return 1;
  43. }
  44. return 0;
  45. }