release.S 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2008-2012 Freescale Semiconductor, Inc.
  4. * Kumar Gala <kumar.gala@freescale.com>
  5. */
  6. #include <asm-offsets.h>
  7. #include <config.h>
  8. #include <mpc85xx.h>
  9. #include <ppc_asm.tmpl>
  10. #include <ppc_defs.h>
  11. #include <asm/cache.h>
  12. #include <asm/mmu.h>
  13. /* To boot secondary cpus, we need a place for them to start up.
  14. * Normally, they start at 0xfffffffc, but that's usually the
  15. * firmware, and we don't want to have to run the firmware again.
  16. * Instead, the primary cpu will set the BPTR to point here to
  17. * this page. We then set up the core, and head to
  18. * start_secondary. Note that this means that the code below
  19. * must never exceed 1023 instructions (the branch at the end
  20. * would then be the 1024th).
  21. */
  22. .globl __secondary_start_page
  23. .align 12
  24. __secondary_start_page:
  25. #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
  26. msync
  27. isync
  28. mfspr r3, SPRN_HDBCR0
  29. oris r3, r3, 0x0080
  30. mtspr SPRN_HDBCR0, r3
  31. #endif
  32. /* First do some preliminary setup */
  33. lis r3, HID0_EMCP@h /* enable machine check */
  34. #ifndef CONFIG_E500MC
  35. ori r3,r3,HID0_TBEN@l /* enable Timebase */
  36. #endif
  37. #ifdef CONFIG_PHYS_64BIT
  38. ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
  39. #endif
  40. mtspr SPRN_HID0,r3
  41. #ifndef CONFIG_E500MC
  42. li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
  43. mfspr r0,PVR
  44. andi. r0,r0,0xff
  45. cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
  46. blt 1f
  47. /* Set MBDD bit also */
  48. ori r3, r3, HID1_MBDD@l
  49. 1:
  50. mtspr SPRN_HID1,r3
  51. #endif
  52. #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  53. mfspr r3,SPRN_HDBCR1
  54. oris r3,r3,0x0100
  55. mtspr SPRN_HDBCR1,r3
  56. #endif
  57. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  58. mfspr r3,SPRN_SVR
  59. rlwinm r3,r3,0,0xff
  60. li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
  61. cmpw r3,r4
  62. beq 1f
  63. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
  64. li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
  65. cmpw r3,r4
  66. beq 1f
  67. #endif
  68. /* Not a supported revision affected by erratum */
  69. b 2f
  70. 1: /* Erratum says set bits 55:60 to 001001 */
  71. msync
  72. isync
  73. mfspr r3,SPRN_HDBCR0
  74. li r4,0x48
  75. rlwimi r3,r4,0,0x1f8
  76. mtspr SPRN_HDBCR0,r3
  77. isync
  78. 2:
  79. #endif
  80. /* Enable branch prediction */
  81. lis r3,BUCSR_ENABLE@h
  82. ori r3,r3,BUCSR_ENABLE@l
  83. mtspr SPRN_BUCSR,r3
  84. /* Ensure TB is 0 */
  85. li r3,0
  86. mttbl r3
  87. mttbu r3
  88. /* Enable/invalidate the I-Cache */
  89. lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
  90. ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
  91. mtspr SPRN_L1CSR1,r2
  92. 1:
  93. mfspr r3,SPRN_L1CSR1
  94. and. r1,r3,r2
  95. bne 1b
  96. lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
  97. ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
  98. mtspr SPRN_L1CSR1,r3
  99. isync
  100. 2:
  101. mfspr r3,SPRN_L1CSR1
  102. andi. r1,r3,L1CSR1_ICE@l
  103. beq 2b
  104. /* Enable/invalidate the D-Cache */
  105. lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
  106. ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
  107. mtspr SPRN_L1CSR0,r2
  108. 1:
  109. mfspr r3,SPRN_L1CSR0
  110. and. r1,r3,r2
  111. bne 1b
  112. lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
  113. ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
  114. mtspr SPRN_L1CSR0,r3
  115. isync
  116. 2:
  117. mfspr r3,SPRN_L1CSR0
  118. andi. r1,r3,L1CSR0_DCE@l
  119. beq 2b
  120. #define toreset(x) (x - __secondary_start_page + 0xfffff000)
  121. /* get our PIR to figure out our table entry */
  122. lis r3,toreset(__spin_table_addr)@h
  123. ori r3,r3,toreset(__spin_table_addr)@l
  124. lwz r3,0(r3)
  125. mfspr r0,SPRN_PIR
  126. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  127. /*
  128. * PIR definition for Chassis 2
  129. * 0-17 Reserved (logic 0s)
  130. * 18-19 CHIP_ID, 2'b00 - SoC 1
  131. * all others - reserved
  132. * 20-24 CLUSTER_ID 5'b00000 - CCM 1
  133. * all others - reserved
  134. * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
  135. * 2'b01 - cluster 2
  136. * 2'b10 - cluster 3
  137. * 2'b11 - cluster 4
  138. * 27-28 CORE_ID 2'b00 - core 0
  139. * 2'b01 - core 1
  140. * 2'b10 - core 2
  141. * 2'b11 - core 3
  142. * 29-31 THREAD_ID 3'b000 - thread 0
  143. * 3'b001 - thread 1
  144. *
  145. * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
  146. * and clusters by 0x20.
  147. *
  148. * We renumber PIR so that all threads in the system are consecutive.
  149. */
  150. rlwinm r8,r0,29,0x03 /* r8 = core within cluster */
  151. srwi r10,r0,5 /* r10 = cluster */
  152. mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
  153. add r5,r5,r8 /* for spin table index */
  154. mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */
  155. #elif defined(CONFIG_E500MC)
  156. rlwinm r4,r0,27,27,31
  157. mr r5,r4
  158. #else
  159. mr r4,r0
  160. mr r5,r4
  161. #endif
  162. /*
  163. * r10 has the base address for the entry.
  164. * we cannot access it yet before setting up a new TLB
  165. */
  166. slwi r8,r5,6 /* spin table is padded to 64 byte */
  167. add r10,r3,r8
  168. mtspr SPRN_PIR,r4 /* write to PIR register */
  169. #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
  170. mfspr r8, L1CSR2
  171. clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */
  172. mtspr L1CSR2, r8
  173. #else
  174. #ifdef CONFIG_SYS_CACHE_STASHING
  175. /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
  176. slwi r8,r4,1
  177. addi r8,r8,32
  178. mtspr L1CSR2,r8
  179. #endif
  180. #endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */
  181. #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
  182. defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
  183. /*
  184. * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
  185. * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
  186. * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
  187. */
  188. mfspr r3,SPRN_SVR
  189. rlwinm r6,r3,24,~0x800 /* clear E bit */
  190. lis r5,SVR_P4080@h
  191. ori r5,r5,SVR_P4080@l
  192. cmpw r6,r5
  193. bne 1f
  194. rlwinm r3,r3,0,0xf0
  195. li r5,0x30
  196. cmpw r3,r5
  197. bge 2f
  198. 1:
  199. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  200. lis r3,toreset(enable_cpu_a011_workaround)@ha
  201. lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
  202. cmpwi r3,0
  203. beq 2f
  204. #endif
  205. mfspr r3,L1CSR2
  206. oris r3,r3,(L1CSR2_DCWS)@h
  207. mtspr L1CSR2,r3
  208. 2:
  209. #endif
  210. #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
  211. /*
  212. * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
  213. * write shadow mode. This code should run after other code setting
  214. * DCWS.
  215. */
  216. mfspr r3,L1CSR2
  217. andis. r3,r3,(L1CSR2_DCWS)@h
  218. beq 1f
  219. mfspr r3, SPRN_HDBCR0
  220. oris r3, r3, 0x8000
  221. mtspr SPRN_HDBCR0, r3
  222. 1:
  223. #endif
  224. #ifdef CONFIG_BACKSIDE_L2_CACHE
  225. /* skip L2 setup on P2040/P2040E as they have no L2 */
  226. mfspr r3,SPRN_SVR
  227. rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
  228. lis r3,SVR_P2040@h
  229. ori r3,r3,SVR_P2040@l
  230. cmpw r6,r3
  231. beq 3f
  232. /* Enable/invalidate the L2 cache */
  233. msync
  234. lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
  235. ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
  236. mtspr SPRN_L2CSR0,r2
  237. 1:
  238. mfspr r3,SPRN_L2CSR0
  239. and. r1,r3,r2
  240. bne 1b
  241. #ifdef CONFIG_SYS_CACHE_STASHING
  242. /* set stash id to (coreID) * 2 + 32 + L2 (1) */
  243. addi r3,r8,1
  244. mtspr SPRN_L2CSR1,r3
  245. #endif
  246. lis r3,CONFIG_SYS_INIT_L2CSR0@h
  247. ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
  248. mtspr SPRN_L2CSR0,r3
  249. isync
  250. 2:
  251. mfspr r3,SPRN_L2CSR0
  252. andis. r1,r3,L2CSR0_L2E@h
  253. beq 2b
  254. #endif
  255. 3:
  256. /* setup mapping for the spin table, WIMGE=0b00100 */
  257. lis r13,toreset(__spin_table_addr)@h
  258. ori r13,r13,toreset(__spin_table_addr)@l
  259. lwz r13,0(r13)
  260. /* mask by 4K */
  261. rlwinm r13,r13,0,0,19
  262. lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
  263. mtspr SPRN_MAS0,r11
  264. lis r11,(MAS1_VALID|MAS1_IPROT)@h
  265. ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
  266. mtspr SPRN_MAS1,r11
  267. oris r11,r13,(MAS2_M|MAS2_G)@h
  268. ori r11,r13,(MAS2_M|MAS2_G)@l
  269. mtspr SPRN_MAS2,r11
  270. oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
  271. ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
  272. mtspr SPRN_MAS3,r11
  273. li r11,0
  274. mtspr SPRN_MAS7,r11
  275. tlbwe
  276. /*
  277. * __bootpg_addr has the address of __second_half_boot_page
  278. * jump there in AS=1 space with cache enabled
  279. */
  280. lis r13,toreset(__bootpg_addr)@h
  281. ori r13,r13,toreset(__bootpg_addr)@l
  282. lwz r11,0(r13)
  283. mtspr SPRN_SRR0,r11
  284. mfmsr r13
  285. ori r12,r13,MSR_IS|MSR_DS@l
  286. mtspr SPRN_SRR1,r12
  287. rfi
  288. /*
  289. * Allocate some space for the SDRAM address of the bootpg.
  290. * This variable has to be in the boot page so that it can
  291. * be accessed by secondary cores when they come out of reset.
  292. */
  293. .align L1_CACHE_SHIFT
  294. .globl __bootpg_addr
  295. __bootpg_addr:
  296. .long 0
  297. .global __spin_table_addr
  298. __spin_table_addr:
  299. .long 0
  300. /*
  301. * This variable is set by cpu_init_r() after parsing hwconfig
  302. * to enable workaround for erratum NMG_CPU_A011.
  303. */
  304. .align L1_CACHE_SHIFT
  305. .global enable_cpu_a011_workaround
  306. enable_cpu_a011_workaround:
  307. .long 1
  308. /* Fill in the empty space. The actual reset vector is
  309. * the last word of the page */
  310. __secondary_start_code_end:
  311. .space 4092 - (__secondary_start_code_end - __secondary_start_page)
  312. __secondary_reset_vector:
  313. b __secondary_start_page
  314. /* this is a separated page for the spin table and cacheable boot code */
  315. .align L1_CACHE_SHIFT
  316. .global __second_half_boot_page
  317. __second_half_boot_page:
  318. #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
  319. lis r3,(spin_table_compat - __second_half_boot_page)@h
  320. ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
  321. add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
  322. lwz r14,0(r3)
  323. #endif
  324. #define ENTRY_ADDR_UPPER 0
  325. #define ENTRY_ADDR_LOWER 4
  326. #define ENTRY_R3_UPPER 8
  327. #define ENTRY_R3_LOWER 12
  328. #define ENTRY_RESV 16
  329. #define ENTRY_PIR 20
  330. #define ENTRY_SIZE 64
  331. /*
  332. * setup the entry
  333. * r10 has the base address of the spin table.
  334. * spin table is defined as
  335. * struct {
  336. * uint64_t entry_addr;
  337. * uint64_t r3;
  338. * uint32_t rsvd1;
  339. * uint32_t pir;
  340. * };
  341. * we pad this struct to 64 bytes so each entry is in its own cacheline
  342. */
  343. li r3,0
  344. li r8,1
  345. mfspr r4,SPRN_PIR
  346. stw r3,ENTRY_ADDR_UPPER(r10)
  347. stw r3,ENTRY_R3_UPPER(r10)
  348. stw r4,ENTRY_R3_LOWER(r10)
  349. stw r3,ENTRY_RESV(r10)
  350. stw r4,ENTRY_PIR(r10)
  351. msync
  352. stw r8,ENTRY_ADDR_LOWER(r10)
  353. /* spin waiting for addr */
  354. 3:
  355. /*
  356. * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
  357. * memory. Old OS may not work with this change. A patch is waiting to be
  358. * accepted for Linux kernel. Other OS needs similar fix to spin table.
  359. * For OSes with old spin table code, we can enable this temporary fix by
  360. * setting environmental variable "spin_table_compat". For new OSes, set
  361. * "spin_table_compat=no". After Linux is fixed, we can remove this macro
  362. * and related code. For now, it is enabled by default.
  363. */
  364. #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
  365. cmpwi r14,0
  366. beq 4f
  367. dcbf 0, r10
  368. sync
  369. 4:
  370. #endif
  371. lwz r4,ENTRY_ADDR_LOWER(r10)
  372. andi. r11,r4,1
  373. bne 3b
  374. isync
  375. /* get the upper bits of the addr */
  376. lwz r11,ENTRY_ADDR_UPPER(r10)
  377. /* setup branch addr */
  378. mtspr SPRN_SRR0,r4
  379. /* mark the entry as released */
  380. li r8,3
  381. stw r8,ENTRY_ADDR_LOWER(r10)
  382. /* mask by ~64M to setup our tlb we will jump to */
  383. rlwinm r12,r4,0,0,5
  384. /*
  385. * setup r3, r4, r5, r6, r7, r8, r9
  386. * r3 contains the value to put in the r3 register at secondary cpu
  387. * entry. The high 32-bits are ignored on 32-bit chip implementations.
  388. * 64-bit chip implementations however shall load all 64-bits
  389. */
  390. #ifdef CONFIG_SYS_PPC64
  391. ld r3,ENTRY_R3_UPPER(r10)
  392. #else
  393. lwz r3,ENTRY_R3_LOWER(r10)
  394. #endif
  395. li r4,0
  396. li r5,0
  397. li r6,0
  398. lis r7,(64*1024*1024)@h
  399. li r8,0
  400. li r9,0
  401. /* load up the pir */
  402. lwz r0,ENTRY_PIR(r10)
  403. mtspr SPRN_PIR,r0
  404. mfspr r0,SPRN_PIR
  405. stw r0,ENTRY_PIR(r10)
  406. mtspr IVPR,r12
  407. /*
  408. * Coming here, we know the cpu has one TLB mapping in TLB1[0]
  409. * which maps 0xfffff000-0xffffffff one-to-one. We set up a
  410. * second mapping that maps addr 1:1 for 64M, and then we jump to
  411. * addr
  412. */
  413. lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
  414. mtspr SPRN_MAS0,r10
  415. lis r10,(MAS1_VALID|MAS1_IPROT)@h
  416. ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
  417. mtspr SPRN_MAS1,r10
  418. /* WIMGE = 0b00000 for now */
  419. mtspr SPRN_MAS2,r12
  420. ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
  421. mtspr SPRN_MAS3,r12
  422. #ifdef CONFIG_ENABLE_36BIT_PHYS
  423. mtspr SPRN_MAS7,r11
  424. #endif
  425. tlbwe
  426. /* Now we have another mapping for this page, so we jump to that
  427. * mapping
  428. */
  429. mtspr SPRN_SRR1,r13
  430. rfi
  431. .align 6
  432. .globl __spin_table
  433. __spin_table:
  434. .space CONFIG_MAX_CPUS*ENTRY_SIZE
  435. #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
  436. .align L1_CACHE_SHIFT
  437. .global spin_table_compat
  438. spin_table_compat:
  439. .long 1
  440. #endif
  441. __spin_table_end:
  442. .space 4096 - (__spin_table_end - __spin_table)