pci.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004 Freescale Semiconductor.
  4. * Copyright (C) 2003 Motorola Inc.
  5. * Xianghua Xiao (x.xiao@motorola.com)
  6. */
  7. /*
  8. * PCI Configuration space access support for MPC85xx PCI Bridge
  9. */
  10. #include <common.h>
  11. #include <asm/bitops.h>
  12. #include <asm/cpm_85xx.h>
  13. #include <pci.h>
  14. #if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI)
  15. #ifndef CONFIG_SYS_PCI1_MEM_BUS
  16. #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
  17. #endif
  18. #ifndef CONFIG_SYS_PCI1_IO_BUS
  19. #define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
  20. #endif
  21. #ifndef CONFIG_SYS_PCI2_MEM_BUS
  22. #define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
  23. #endif
  24. #ifndef CONFIG_SYS_PCI2_IO_BUS
  25. #define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
  26. #endif
  27. static struct pci_controller *pci_hose;
  28. void
  29. pci_mpc85xx_init(struct pci_controller *board_hose)
  30. {
  31. u16 reg16;
  32. u32 dev;
  33. volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
  34. #ifdef CONFIG_MPC85XX_PCI2
  35. volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
  36. #endif
  37. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  38. struct pci_controller * hose;
  39. pci_hose = board_hose;
  40. hose = &pci_hose[0];
  41. hose->first_busno = 0;
  42. hose->last_busno = 0xff;
  43. pci_setup_indirect(hose,
  44. (CONFIG_SYS_IMMR+0x8000),
  45. (CONFIG_SYS_IMMR+0x8004));
  46. /*
  47. * Hose scan.
  48. */
  49. dev = PCI_BDF(hose->first_busno, 0, 0);
  50. pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
  51. reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  52. pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  53. /*
  54. * Clear non-reserved bits in status register.
  55. */
  56. pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  57. if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
  58. /* PCI-X init */
  59. if (CONFIG_SYS_CLK_FREQ < 66000000)
  60. printf("PCI-X will only work at 66 MHz\n");
  61. reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
  62. | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
  63. pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
  64. }
  65. pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
  66. pcix->potear1 = 0x00000000;
  67. pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
  68. pcix->powbear1 = 0x00000000;
  69. pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
  70. POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
  71. pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
  72. pcix->potear2 = 0x00000000;
  73. pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
  74. pcix->powbear2 = 0x00000000;
  75. pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
  76. POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
  77. pcix->pitar1 = 0x00000000;
  78. pcix->piwbar1 = 0x00000000;
  79. pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  80. PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
  81. pcix->powar3 = 0;
  82. pcix->powar4 = 0;
  83. pcix->piwar2 = 0;
  84. pcix->piwar3 = 0;
  85. pci_set_region(hose->regions + 0,
  86. CONFIG_SYS_PCI1_MEM_BUS,
  87. CONFIG_SYS_PCI1_MEM_PHYS,
  88. CONFIG_SYS_PCI1_MEM_SIZE,
  89. PCI_REGION_MEM);
  90. pci_set_region(hose->regions + 1,
  91. CONFIG_SYS_PCI1_IO_BUS,
  92. CONFIG_SYS_PCI1_IO_PHYS,
  93. CONFIG_SYS_PCI1_IO_SIZE,
  94. PCI_REGION_IO);
  95. hose->region_count = 2;
  96. pci_register_hose(hose);
  97. #if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
  98. /*
  99. * This is a SW workaround for an apparent HW problem
  100. * in the PCI controller on the MPC85555/41 CDS boards.
  101. * The first config cycle must be to a valid, known
  102. * device on the PCI bus in order to trick the PCI
  103. * controller state machine into a known valid state.
  104. * Without this, the first config cycle has the chance
  105. * of hanging the controller permanently, just leaving
  106. * it in a semi-working state, or leaving it working.
  107. *
  108. * Pick on the Tundra, Device 17, to get it right.
  109. */
  110. {
  111. u8 header_type;
  112. pci_hose_read_config_byte(hose,
  113. PCI_BDF(0,BRIDGE_ID,0),
  114. PCI_HEADER_TYPE,
  115. &header_type);
  116. }
  117. #endif
  118. hose->last_busno = pci_hose_scan(hose);
  119. #ifdef CONFIG_MPC85XX_PCI2
  120. hose = &pci_hose[1];
  121. hose->first_busno = pci_hose[0].last_busno + 1;
  122. hose->last_busno = 0xff;
  123. pci_setup_indirect(hose,
  124. (CONFIG_SYS_IMMR+0x9000),
  125. (CONFIG_SYS_IMMR+0x9004));
  126. dev = PCI_BDF(hose->first_busno, 0, 0);
  127. pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
  128. reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  129. pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  130. /*
  131. * Clear non-reserved bits in status register.
  132. */
  133. pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  134. pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
  135. pcix2->potear1 = 0x00000000;
  136. pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
  137. pcix2->powbear1 = 0x00000000;
  138. pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
  139. POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
  140. pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
  141. pcix2->potear2 = 0x00000000;
  142. pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
  143. pcix2->powbear2 = 0x00000000;
  144. pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
  145. POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
  146. pcix2->pitar1 = 0x00000000;
  147. pcix2->piwbar1 = 0x00000000;
  148. pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  149. PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
  150. pcix2->powar3 = 0;
  151. pcix2->powar4 = 0;
  152. pcix2->piwar2 = 0;
  153. pcix2->piwar3 = 0;
  154. pci_set_region(hose->regions + 0,
  155. CONFIG_SYS_PCI2_MEM_BUS,
  156. CONFIG_SYS_PCI2_MEM_PHYS,
  157. CONFIG_SYS_PCI2_MEM_SIZE,
  158. PCI_REGION_MEM);
  159. pci_set_region(hose->regions + 1,
  160. CONFIG_SYS_PCI2_IO_BUS,
  161. CONFIG_SYS_PCI2_IO_PHYS,
  162. CONFIG_SYS_PCI2_IO_SIZE,
  163. PCI_REGION_IO);
  164. hose->region_count = 2;
  165. /*
  166. * Hose scan.
  167. */
  168. pci_register_hose(hose);
  169. hose->last_busno = pci_hose_scan(hose);
  170. #endif
  171. }
  172. #endif /* !CONFIG_FSL_PCI_INIT */