p3041_serdes.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/fsl_serdes.h>
  7. #include <asm/processor.h>
  8. #include <asm/io.h>
  9. #include "fsl_corenet_serdes.h"
  10. static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
  11. [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
  12. PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
  13. SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
  14. [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
  15. PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
  16. SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
  17. [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
  18. PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
  19. SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
  20. [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
  21. AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
  22. NONE, NONE, SATA1, SATA2, },
  23. [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
  24. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  25. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
  26. [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
  27. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  28. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
  29. XAUI_FM1, XAUI_FM1, },
  30. [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
  31. AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
  32. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
  33. SGMII_FM1_DTSEC4, },
  34. [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
  35. AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
  36. NONE, NONE, SATA1, SATA2, },
  37. [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
  38. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  39. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
  40. SRIO1, },
  41. [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
  42. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  43. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
  44. [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
  45. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  46. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
  47. NONE, NONE, },
  48. [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
  49. AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
  50. NONE, NONE, SATA1, SATA2, },
  51. [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
  52. AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
  53. SATA1, SATA2, },
  54. [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
  55. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  56. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
  57. XAUI_FM1, XAUI_FM1, },
  58. [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
  59. AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
  60. SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
  61. SGMII_FM1_DTSEC4, },
  62. [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
  63. AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
  64. NONE, NONE, SATA1, SATA2, },
  65. [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
  66. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  67. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
  68. [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
  69. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  70. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
  71. NONE, NONE, },
  72. [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
  73. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  74. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
  75. [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
  76. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  77. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
  78. NONE, NONE, },
  79. [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
  80. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  81. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
  82. XAUI_FM1, XAUI_FM1, },
  83. [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
  84. AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
  85. NONE, NONE, SATA1, SATA2, },
  86. [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
  87. AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
  88. NONE, NONE, SATA1, SATA2, },
  89. [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
  90. AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  91. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
  92. NONE, NONE, },
  93. [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
  94. AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
  95. NONE, NONE, SATA1, SATA2, },
  96. [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
  97. SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
  98. AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
  99. NONE, SATA1, SATA2, },
  100. [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
  101. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
  102. XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
  103. [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
  104. SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
  105. AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
  106. NONE, SATA1, SATA2, },
  107. [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
  108. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
  109. XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
  110. };
  111. enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
  112. {
  113. if (!serdes_lane_enabled(lane))
  114. return NONE;
  115. return serdes_cfg_tbl[cfg][lane];
  116. }
  117. int is_serdes_prtcl_valid(u32 prtcl) {
  118. int i;
  119. if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
  120. return 0;
  121. for (i = 0; i < SRDS_MAX_LANES; i++) {
  122. if (serdes_cfg_tbl[prtcl][i] != NONE)
  123. return 1;
  124. }
  125. return 0;
  126. }