p1021_serdes.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <config.h>
  6. #include <common.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <asm/immap_85xx.h>
  10. #include <asm/fsl_serdes.h>
  11. #include <linux/delay.h>
  12. typedef struct serdes_85xx {
  13. u32 srdscr0; /* 0x00 - SRDS Control Register 0 */
  14. u32 srdscr1; /* 0x04 - SRDS Control Register 1 */
  15. u32 srdscr2; /* 0x08 - SRDS Control Register 2 */
  16. u32 srdscr3; /* 0x0C - SRDS Control Register 3 */
  17. u32 srdscr4; /* 0x10 - SRDS Control Register 4 */
  18. } serdes_85xx_t;
  19. #define FSL_SRDSCR3_EIC0(x) (((x) & 0x1f) << 8)
  20. #define FSL_SRDSCR3_EIC0_MASK FSL_SRDSCR3_EIC0(0x1f)
  21. #define FSL_SRDSCR3_EIC1(x) (((x) & 0x1f) << 0)
  22. #define FSL_SRDSCR3_EIC1_MASK FSL_SRDSCR3_EIC1(0x1f)
  23. #define FSL_SRDSCR4_EIC2(x) (((x) & 0x1f) << 8)
  24. #define FSL_SRDSCR4_EIC2_MASK FSL_SRDSCR4_EIC2(0x1f)
  25. #define FSL_SRDSCR4_EIC3(x) (((x) & 0x1f) << 0)
  26. #define FSL_SRDSCR4_EIC3_MASK FSL_SRDSCR4_EIC3(0x1f)
  27. #define EIC_PCIE 0x13
  28. #define EIC_SGMII 0x04
  29. #define SRDS1_MAX_LANES 4
  30. static u32 serdes1_prtcl_map;
  31. static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  32. [0x0] = {PCIE1, NONE, NONE, NONE},
  33. [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
  34. [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
  35. [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
  36. };
  37. int is_serdes_configured(enum srds_prtcl prtcl)
  38. {
  39. if (!(serdes1_prtcl_map & (1 << NONE)))
  40. fsl_serdes_init();
  41. return (1 << prtcl) & serdes1_prtcl_map;
  42. }
  43. void fsl_serdes_init(void)
  44. {
  45. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  46. serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
  47. u32 pordevsr = in_be32(&gur->pordevsr);
  48. u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  49. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  50. int lane;
  51. u32 mask, val;
  52. if (serdes1_prtcl_map & (1 << NONE))
  53. return;
  54. debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
  55. if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  56. printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  57. return;
  58. }
  59. for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  60. enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
  61. serdes1_prtcl_map |= (1 << lane_prtcl);
  62. }
  63. /* Set the first bit to indicate serdes has been initialized */
  64. serdes1_prtcl_map |= (1 << NONE);
  65. /* Init SERDES Receiver electrical idle detection control for PCIe */
  66. /* Lane 0 is always PCIe 1 */
  67. mask = FSL_SRDSCR3_EIC0_MASK;
  68. val = FSL_SRDSCR3_EIC0(EIC_PCIE);
  69. /* Lane 1 */
  70. if ((serdes1_cfg_tbl[srds_cfg][1] == PCIE1) ||
  71. (serdes1_cfg_tbl[srds_cfg][1] == PCIE2)) {
  72. mask |= FSL_SRDSCR3_EIC1_MASK;
  73. val |= FSL_SRDSCR3_EIC1(EIC_PCIE);
  74. }
  75. /* Handle lanes 0 & 1 */
  76. clrsetbits_be32(&serdes->srdscr3, mask, val);
  77. /* Handle lanes 2 & 3 */
  78. if (srds_cfg == 0x6) {
  79. mask = FSL_SRDSCR4_EIC2_MASK | FSL_SRDSCR4_EIC3_MASK;
  80. val = FSL_SRDSCR4_EIC2(EIC_PCIE) | FSL_SRDSCR4_EIC3(EIC_PCIE);
  81. clrsetbits_be32(&serdes->srdscr4, mask, val);
  82. }
  83. /* 100 ms delay */
  84. udelay(100000);
  85. }