mpc8544_serdes.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010 Freescale Semiconductor, Inc.
  4. */
  5. #include <config.h>
  6. #include <common.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <asm/immap_85xx.h>
  10. #include <asm/fsl_serdes.h>
  11. #define SRDS1_MAX_LANES 8
  12. #define SRDS2_MAX_LANES 4
  13. static u32 serdes1_prtcl_map, serdes2_prtcl_map;
  14. static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  15. [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
  16. [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
  17. [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  18. [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  19. [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  20. [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  21. };
  22. static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
  23. [0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
  24. [0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
  25. [0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
  26. [0x6] = {PCIE3, NONE, NONE, NONE},
  27. [0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3},
  28. };
  29. int is_serdes_configured(enum srds_prtcl device)
  30. {
  31. int ret;
  32. if (!(serdes1_prtcl_map & (1 << NONE)))
  33. fsl_serdes_init();
  34. ret = (1 << device) & serdes1_prtcl_map;
  35. if (ret)
  36. return ret;
  37. if (!(serdes2_prtcl_map & (1 << NONE)))
  38. fsl_serdes_init();
  39. return (1 << device) & serdes2_prtcl_map;
  40. }
  41. void fsl_serdes_init(void)
  42. {
  43. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  44. u32 pordevsr = in_be32(&gur->pordevsr);
  45. u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  46. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  47. int lane;
  48. if (serdes1_prtcl_map & (1 << NONE) &&
  49. serdes2_prtcl_map & (1 << NONE))
  50. return;
  51. debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
  52. if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  53. printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  54. return;
  55. }
  56. for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  57. enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
  58. serdes1_prtcl_map |= (1 << lane_prtcl);
  59. }
  60. /* Set the first bit to indicate serdes has been initialized */
  61. serdes1_prtcl_map |= (1 << NONE);
  62. if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
  63. printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  64. return;
  65. }
  66. for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
  67. enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
  68. serdes2_prtcl_map |= (1 << lane_prtcl);
  69. }
  70. if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)
  71. serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);
  72. if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
  73. serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);
  74. /* Set the first bit to indicate serdes has been initialized */
  75. serdes2_prtcl_map |= (1 << NONE);
  76. }