mpc8536_serdes.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008,2010 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. */
  6. #include <config.h>
  7. #include <common.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <asm/immap_85xx.h>
  11. #include <asm/fsl_serdes.h>
  12. /* PORDEVSR register */
  13. #define GUTS_PORDEVSR_OFFS 0xc
  14. #define GUTS_PORDEVSR_SERDES2_IO_SEL 0x38000000
  15. #define GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT 27
  16. /* SerDes CR0 register */
  17. #define FSL_SRDSCR0_OFFS 0x0
  18. #define FSL_SRDSCR0_TXEQA_MASK 0x00007000
  19. #define FSL_SRDSCR0_TXEQA_SGMII 0x00004000
  20. #define FSL_SRDSCR0_TXEQA_SATA 0x00001000
  21. #define FSL_SRDSCR0_TXEQE_MASK 0x00000700
  22. #define FSL_SRDSCR0_TXEQE_SGMII 0x00000400
  23. #define FSL_SRDSCR0_TXEQE_SATA 0x00000100
  24. /* SerDes CR1 register */
  25. #define FSL_SRDSCR1_OFFS 0x4
  26. #define FSL_SRDSCR1_LANEA_MASK 0x80200000
  27. #define FSL_SRDSCR1_LANEA_OFF 0x80200000
  28. #define FSL_SRDSCR1_LANEE_MASK 0x08020000
  29. #define FSL_SRDSCR1_LANEE_OFF 0x08020000
  30. /* SerDes CR2 register */
  31. #define FSL_SRDSCR2_OFFS 0x8
  32. #define FSL_SRDSCR2_EICA_MASK 0x00001f00
  33. #define FSL_SRDSCR2_EICA_SGMII 0x00000400
  34. #define FSL_SRDSCR2_EICA_SATA 0x00001400
  35. #define FSL_SRDSCR2_EICE_MASK 0x0000001f
  36. #define FSL_SRDSCR2_EICE_SGMII 0x00000004
  37. #define FSL_SRDSCR2_EICE_SATA 0x00000014
  38. /* SerDes CR3 register */
  39. #define FSL_SRDSCR3_OFFS 0xc
  40. #define FSL_SRDSCR3_LANEA_MASK 0x3f000700
  41. #define FSL_SRDSCR3_LANEA_SGMII 0x00000000
  42. #define FSL_SRDSCR3_LANEA_SATA 0x15000500
  43. #define FSL_SRDSCR3_LANEE_MASK 0x003f0007
  44. #define FSL_SRDSCR3_LANEE_SGMII 0x00000000
  45. #define FSL_SRDSCR3_LANEE_SATA 0x00150005
  46. #define SRDS1_MAX_LANES 8
  47. #define SRDS2_MAX_LANES 2
  48. static u32 serdes1_prtcl_map, serdes2_prtcl_map;
  49. static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  50. [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
  51. [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
  52. [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
  53. [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
  54. };
  55. static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
  56. [0x1] = {SATA1, SATA2},
  57. [0x3] = {SATA1, NONE},
  58. [0x4] = {SGMII_TSEC1, SGMII_TSEC3},
  59. [0x6] = {SGMII_TSEC1, NONE},
  60. };
  61. int is_serdes_configured(enum srds_prtcl device)
  62. {
  63. int ret;
  64. if (!(serdes1_prtcl_map & (1 << NONE)))
  65. fsl_serdes_init();
  66. ret = (1 << device) & serdes1_prtcl_map;
  67. if (ret)
  68. return ret;
  69. if (!(serdes2_prtcl_map & (1 << NONE)))
  70. fsl_serdes_init();
  71. return (1 << device) & serdes2_prtcl_map;
  72. }
  73. void fsl_serdes_init(void)
  74. {
  75. void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  76. void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
  77. u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
  78. u32 srds1_io_sel, srds2_io_sel;
  79. u32 tmp;
  80. int lane;
  81. if (serdes1_prtcl_map & (1 << NONE) &&
  82. serdes2_prtcl_map & (1 << NONE))
  83. return;
  84. srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  85. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  86. /* parse the SRDS2_IO_SEL of PORDEVSR */
  87. srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
  88. >> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
  89. debug("PORDEVSR[SRDS1_IO_SEL] = %x\n", srds1_io_sel);
  90. debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_io_sel);
  91. switch (srds2_io_sel) {
  92. case 1: /* Lane A - SATA1, Lane E - SATA2 */
  93. /* CR 0 */
  94. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  95. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  96. tmp |= FSL_SRDSCR0_TXEQA_SATA;
  97. tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
  98. tmp |= FSL_SRDSCR0_TXEQE_SATA;
  99. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  100. /* CR 1 */
  101. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  102. tmp &= ~FSL_SRDSCR1_LANEA_MASK;
  103. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  104. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  105. /* CR 2 */
  106. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  107. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  108. tmp |= FSL_SRDSCR2_EICA_SATA;
  109. tmp &= ~FSL_SRDSCR2_EICE_MASK;
  110. tmp |= FSL_SRDSCR2_EICE_SATA;
  111. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  112. /* CR 3 */
  113. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  114. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  115. tmp |= FSL_SRDSCR3_LANEA_SATA;
  116. tmp &= ~FSL_SRDSCR3_LANEE_MASK;
  117. tmp |= FSL_SRDSCR3_LANEE_SATA;
  118. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  119. break;
  120. case 3: /* Lane A - SATA1, Lane E - disabled */
  121. /* CR 0 */
  122. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  123. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  124. tmp |= FSL_SRDSCR0_TXEQA_SATA;
  125. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  126. /* CR 1 */
  127. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  128. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  129. tmp |= FSL_SRDSCR1_LANEE_OFF;
  130. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  131. /* CR 2 */
  132. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  133. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  134. tmp |= FSL_SRDSCR2_EICA_SATA;
  135. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  136. /* CR 3 */
  137. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  138. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  139. tmp |= FSL_SRDSCR3_LANEA_SATA;
  140. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  141. break;
  142. case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */
  143. /* CR 0 */
  144. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  145. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  146. tmp |= FSL_SRDSCR0_TXEQA_SGMII;
  147. tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
  148. tmp |= FSL_SRDSCR0_TXEQE_SGMII;
  149. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  150. /* CR 1 */
  151. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  152. tmp &= ~FSL_SRDSCR1_LANEA_MASK;
  153. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  154. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  155. /* CR 2 */
  156. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  157. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  158. tmp |= FSL_SRDSCR2_EICA_SGMII;
  159. tmp &= ~FSL_SRDSCR2_EICE_MASK;
  160. tmp |= FSL_SRDSCR2_EICE_SGMII;
  161. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  162. /* CR 3 */
  163. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  164. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  165. tmp |= FSL_SRDSCR3_LANEA_SGMII;
  166. tmp &= ~FSL_SRDSCR3_LANEE_MASK;
  167. tmp |= FSL_SRDSCR3_LANEE_SGMII;
  168. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  169. break;
  170. case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */
  171. /* CR 0 */
  172. tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
  173. tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
  174. tmp |= FSL_SRDSCR0_TXEQA_SGMII;
  175. out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
  176. /* CR 1 */
  177. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  178. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  179. tmp |= FSL_SRDSCR1_LANEE_OFF;
  180. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  181. /* CR 2 */
  182. tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
  183. tmp &= ~FSL_SRDSCR2_EICA_MASK;
  184. tmp |= FSL_SRDSCR2_EICA_SGMII;
  185. out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
  186. /* CR 3 */
  187. tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
  188. tmp &= ~FSL_SRDSCR3_LANEA_MASK;
  189. tmp |= FSL_SRDSCR3_LANEA_SGMII;
  190. out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
  191. break;
  192. case 7: /* Lane A - disabled, Lane E - disabled */
  193. /* CR 1 */
  194. tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
  195. tmp &= ~FSL_SRDSCR1_LANEA_MASK;
  196. tmp |= FSL_SRDSCR1_LANEA_OFF;
  197. tmp &= ~FSL_SRDSCR1_LANEE_MASK;
  198. tmp |= FSL_SRDSCR1_LANEE_OFF;
  199. out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
  200. break;
  201. default:
  202. break;
  203. }
  204. if (srds1_io_sel >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  205. printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
  206. return;
  207. }
  208. for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  209. enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane];
  210. serdes1_prtcl_map |= (1 << lane_prtcl);
  211. }
  212. /* Set the first bit to indicate serdes has been initialized */
  213. serdes1_prtcl_map |= (1 << NONE);
  214. if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) {
  215. printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
  216. return;
  217. }
  218. for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
  219. enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane];
  220. serdes2_prtcl_map |= (1 << lane_prtcl);
  221. }
  222. /* Set the first bit to indicate serdes has been initialized */
  223. serdes2_prtcl_map |= (1 << NONE);
  224. }