interrupts.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. *
  6. * (C) Copyright 2002 (440 port)
  7. * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
  8. *
  9. * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
  10. * Xianghua Xiao (X.Xiao@motorola.com)
  11. */
  12. #include <common.h>
  13. #include <irq_func.h>
  14. #include <log.h>
  15. #include <time.h>
  16. #include <watchdog.h>
  17. #include <command.h>
  18. #include <asm/processor.h>
  19. #include <asm/io.h>
  20. #ifdef CONFIG_POST
  21. #include <post.h>
  22. #endif
  23. #include <asm/ptrace.h>
  24. void interrupt_init_cpu(unsigned *decrementer_count)
  25. {
  26. ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
  27. #ifdef CONFIG_POST
  28. /*
  29. * The POST word is stored in the PIC's TFRR register which gets
  30. * cleared when the PIC is reset. Save it off so we can restore it
  31. * later.
  32. */
  33. ulong post_word = post_word_load();
  34. #endif
  35. out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
  36. while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
  37. ;
  38. out_be32(&pic->gcr, MPC85xx_PICGCR_M);
  39. in_be32(&pic->gcr);
  40. *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
  41. /* PIE is same as DIE, dec interrupt enable */
  42. mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE);
  43. #ifdef CONFIG_INTERRUPTS
  44. pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
  45. debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
  46. pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
  47. debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
  48. pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
  49. debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
  50. #ifdef CONFIG_PCI1
  51. pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
  52. debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
  53. #endif
  54. #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
  55. pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
  56. debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
  57. #endif
  58. #ifdef CONFIG_PCIE1
  59. pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
  60. debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
  61. #endif
  62. #ifdef CONFIG_PCIE3
  63. pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
  64. debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
  65. #endif
  66. pic->ctpr=0; /* 40080 clear current task priority register */
  67. #endif
  68. #ifdef CONFIG_POST
  69. post_word_store(post_word);
  70. #endif
  71. }
  72. /* Install and free a interrupt handler. Not implemented yet. */
  73. void
  74. irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
  75. {
  76. return;
  77. }
  78. void
  79. irq_free_handler(int vec)
  80. {
  81. return;
  82. }
  83. void timer_interrupt_cpu(struct pt_regs *regs)
  84. {
  85. /* PIS is same as DIS, dec interrupt status */
  86. mtspr(SPRN_TSR, TSR_PIS);
  87. }
  88. #if defined(CONFIG_CMD_IRQ)
  89. /* irqinfo - print information about PCI devices,not implemented. */
  90. int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  91. {
  92. return 0;
  93. }
  94. #endif