fdt.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2000
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <env.h>
  11. #include <log.h>
  12. #include <time.h>
  13. #include <linux/libfdt.h>
  14. #include <fdt_support.h>
  15. #include <asm/processor.h>
  16. #include <linux/ctype.h>
  17. #include <asm/io.h>
  18. #include <asm/fsl_fdt.h>
  19. #include <asm/fsl_portals.h>
  20. #include <fsl_qbman.h>
  21. #include <hwconfig.h>
  22. #ifdef CONFIG_FSL_ESDHC
  23. #include <fsl_esdhc.h>
  24. #endif
  25. #ifdef CONFIG_SYS_DPAA_FMAN
  26. #include <fsl_fman.h>
  27. #endif
  28. DECLARE_GLOBAL_DATA_PTR;
  29. extern void ft_qe_setup(void *blob);
  30. extern void ft_fixup_num_cores(void *blob);
  31. extern void ft_srio_setup(void *blob);
  32. #ifdef CONFIG_MP
  33. #include "mp.h"
  34. void ft_fixup_cpu(void *blob, u64 memory_limit)
  35. {
  36. int off;
  37. phys_addr_t spin_tbl_addr = get_spin_phys_addr();
  38. u32 bootpg = determine_mp_bootpg(NULL);
  39. u32 id = get_my_id();
  40. const char *enable_method;
  41. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  42. int ret;
  43. int tdm_hwconfig_enabled = 0;
  44. char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  45. #endif
  46. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  47. while (off != -FDT_ERR_NOTFOUND) {
  48. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  49. if (reg) {
  50. u32 phys_cpu_id = thread_to_core(*reg);
  51. u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
  52. val = cpu_to_fdt64(val);
  53. if (*reg == id) {
  54. fdt_setprop_string(blob, off, "status",
  55. "okay");
  56. } else {
  57. fdt_setprop_string(blob, off, "status",
  58. "disabled");
  59. }
  60. if (hold_cores_in_reset(0)) {
  61. #ifdef CONFIG_FSL_CORENET
  62. /* Cores held in reset, use BRR to release */
  63. enable_method = "fsl,brr-holdoff";
  64. #else
  65. /* Cores held in reset, use EEBPCR to release */
  66. enable_method = "fsl,eebpcr-holdoff";
  67. #endif
  68. } else {
  69. /* Cores out of reset and in a spin-loop */
  70. enable_method = "spin-table";
  71. fdt_setprop(blob, off, "cpu-release-addr",
  72. &val, sizeof(val));
  73. }
  74. fdt_setprop_string(blob, off, "enable-method",
  75. enable_method);
  76. } else {
  77. printf ("cpu NULL\n");
  78. }
  79. off = fdt_node_offset_by_prop_value(blob, off,
  80. "device_type", "cpu", 4);
  81. }
  82. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  83. #define CONFIG_MEM_HOLE_16M 0x1000000
  84. /*
  85. * Extract hwconfig from environment.
  86. * Search for tdm entry in hwconfig.
  87. */
  88. ret = env_get_f("hwconfig", buffer, sizeof(buffer));
  89. if (ret > 0)
  90. tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
  91. /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
  92. if (tdm_hwconfig_enabled) {
  93. off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
  94. CONFIG_MEM_HOLE_16M);
  95. if (off < 0)
  96. printf("Failed to reserve memory for tdm: %s\n",
  97. fdt_strerror(off));
  98. }
  99. #endif
  100. /* Reserve the boot page so OSes dont use it */
  101. if ((u64)bootpg < memory_limit) {
  102. off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
  103. if (off < 0)
  104. printf("Failed to reserve memory for bootpg: %s\n",
  105. fdt_strerror(off));
  106. }
  107. #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
  108. /*
  109. * Reserve the default boot page so OSes dont use it.
  110. * The default boot page is always mapped to bootpg above using
  111. * boot page translation.
  112. */
  113. if (0xfffff000ull < memory_limit) {
  114. off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
  115. if (off < 0) {
  116. printf("Failed to reserve memory for 0xfffff000: %s\n",
  117. fdt_strerror(off));
  118. }
  119. }
  120. #endif
  121. /* Reserve spin table page */
  122. if (spin_tbl_addr < memory_limit) {
  123. off = fdt_add_mem_rsv(blob,
  124. (spin_tbl_addr & ~0xffful), 4096);
  125. if (off < 0)
  126. printf("Failed to reserve memory for spin table: %s\n",
  127. fdt_strerror(off));
  128. }
  129. #ifdef CONFIG_DEEP_SLEEP
  130. #ifdef CONFIG_SPL_MMC_BOOT
  131. off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
  132. CONFIG_SYS_MMC_U_BOOT_SIZE);
  133. if (off < 0)
  134. printf("Failed to reserve memory for SD deep sleep: %s\n",
  135. fdt_strerror(off));
  136. #elif defined(CONFIG_SPL_SPI_BOOT)
  137. off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
  138. CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
  139. if (off < 0)
  140. printf("Failed to reserve memory for SPI deep sleep: %s\n",
  141. fdt_strerror(off));
  142. #endif
  143. #endif
  144. }
  145. #endif
  146. #ifdef CONFIG_SYS_FSL_CPC
  147. static inline void ft_fixup_l3cache(void *blob, int off)
  148. {
  149. u32 line_size, num_ways, size, num_sets;
  150. cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
  151. u32 cfg0 = in_be32(&cpc->cpccfg0);
  152. size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
  153. num_ways = CPC_CFG0_NUM_WAYS(cfg0);
  154. line_size = CPC_CFG0_LINE_SZ(cfg0);
  155. num_sets = size / (line_size * num_ways);
  156. fdt_setprop(blob, off, "cache-unified", NULL, 0);
  157. fdt_setprop_cell(blob, off, "cache-block-size", line_size);
  158. fdt_setprop_cell(blob, off, "cache-size", size);
  159. fdt_setprop_cell(blob, off, "cache-sets", num_sets);
  160. fdt_setprop_cell(blob, off, "cache-level", 3);
  161. #ifdef CONFIG_SYS_CACHE_STASHING
  162. fdt_setprop_cell(blob, off, "cache-stash-id", 1);
  163. #endif
  164. }
  165. #else
  166. #define ft_fixup_l3cache(x, y)
  167. #endif
  168. #if defined(CONFIG_L2_CACHE) || \
  169. defined(CONFIG_BACKSIDE_L2_CACHE) || \
  170. defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
  171. static inline void ft_fixup_l2cache_compatible(void *blob, int off)
  172. {
  173. int len;
  174. struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
  175. if (cpu) {
  176. char buf[40];
  177. if (isdigit(cpu->name[0])) {
  178. /* MPCxxxx, where xxxx == 4-digit number */
  179. len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
  180. cpu->name) + 1;
  181. } else {
  182. /* Pxxxx or Txxxx, where xxxx == 4-digit number */
  183. len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
  184. tolower(cpu->name[0]), cpu->name + 1) + 1;
  185. }
  186. /*
  187. * append "cache" after the NULL character that the previous
  188. * sprintf wrote. This is how a device tree stores multiple
  189. * strings in a property.
  190. */
  191. len += sprintf(buf + len, "cache") + 1;
  192. fdt_setprop(blob, off, "compatible", buf, len);
  193. }
  194. }
  195. #endif
  196. #if defined(CONFIG_L2_CACHE)
  197. /* return size in kilobytes */
  198. static inline u32 l2cache_size(void)
  199. {
  200. volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  201. volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
  202. u32 ver = SVR_SOC_VER(get_svr());
  203. switch (l2siz_field) {
  204. case 0x0:
  205. break;
  206. case 0x1:
  207. if (ver == SVR_8540 || ver == SVR_8560 ||
  208. ver == SVR_8541 || ver == SVR_8555)
  209. return 128;
  210. else
  211. return 256;
  212. break;
  213. case 0x2:
  214. if (ver == SVR_8540 || ver == SVR_8560 ||
  215. ver == SVR_8541 || ver == SVR_8555)
  216. return 256;
  217. else
  218. return 512;
  219. break;
  220. case 0x3:
  221. return 1024;
  222. break;
  223. }
  224. return 0;
  225. }
  226. static inline void ft_fixup_l2cache(void *blob)
  227. {
  228. int off;
  229. u32 *ph;
  230. const u32 line_size = 32;
  231. const u32 num_ways = 8;
  232. const u32 size = l2cache_size() * 1024;
  233. const u32 num_sets = size / (line_size * num_ways);
  234. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  235. if (off < 0) {
  236. debug("no cpu node fount\n");
  237. return;
  238. }
  239. ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
  240. if (ph == NULL) {
  241. debug("no next-level-cache property\n");
  242. return ;
  243. }
  244. off = fdt_node_offset_by_phandle(blob, *ph);
  245. if (off < 0) {
  246. printf("%s: %s\n", __func__, fdt_strerror(off));
  247. return ;
  248. }
  249. ft_fixup_l2cache_compatible(blob, off);
  250. fdt_setprop(blob, off, "cache-unified", NULL, 0);
  251. fdt_setprop_cell(blob, off, "cache-block-size", line_size);
  252. fdt_setprop_cell(blob, off, "cache-size", size);
  253. fdt_setprop_cell(blob, off, "cache-sets", num_sets);
  254. fdt_setprop_cell(blob, off, "cache-level", 2);
  255. /* we dont bother w/L3 since no platform of this type has one */
  256. }
  257. #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
  258. defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
  259. static inline void ft_fixup_l2cache(void *blob)
  260. {
  261. int off, l2_off, l3_off = -1;
  262. u32 *ph;
  263. #ifdef CONFIG_BACKSIDE_L2_CACHE
  264. u32 l2cfg0 = mfspr(SPRN_L2CFG0);
  265. #else
  266. struct ccsr_cluster_l2 *l2cache =
  267. (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
  268. u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
  269. #endif
  270. u32 size, line_size, num_ways, num_sets;
  271. int has_l2 = 1;
  272. /* P2040/P2040E has no L2, so dont set any L2 props */
  273. if (SVR_SOC_VER(get_svr()) == SVR_P2040)
  274. has_l2 = 0;
  275. size = (l2cfg0 & 0x3fff) * 64 * 1024;
  276. num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
  277. line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
  278. num_sets = size / (line_size * num_ways);
  279. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  280. while (off != -FDT_ERR_NOTFOUND) {
  281. ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
  282. if (ph == NULL) {
  283. debug("no next-level-cache property\n");
  284. goto next;
  285. }
  286. l2_off = fdt_node_offset_by_phandle(blob, *ph);
  287. if (l2_off < 0) {
  288. printf("%s: %s\n", __func__, fdt_strerror(off));
  289. goto next;
  290. }
  291. if (has_l2) {
  292. #ifdef CONFIG_SYS_CACHE_STASHING
  293. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  294. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  295. /* Only initialize every eighth thread */
  296. if (reg && !((*reg) % 8)) {
  297. fdt_setprop_cell(blob, l2_off, "cache-stash-id",
  298. (*reg / 4) + 32 + 1);
  299. }
  300. #else
  301. if (reg) {
  302. fdt_setprop_cell(blob, l2_off, "cache-stash-id",
  303. (*reg * 2) + 32 + 1);
  304. }
  305. #endif
  306. #endif
  307. fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
  308. fdt_setprop_cell(blob, l2_off, "cache-block-size",
  309. line_size);
  310. fdt_setprop_cell(blob, l2_off, "cache-size", size);
  311. fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
  312. fdt_setprop_cell(blob, l2_off, "cache-level", 2);
  313. ft_fixup_l2cache_compatible(blob, l2_off);
  314. }
  315. if (l3_off < 0) {
  316. ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
  317. if (ph == NULL) {
  318. debug("no next-level-cache property\n");
  319. goto next;
  320. }
  321. l3_off = *ph;
  322. }
  323. next:
  324. off = fdt_node_offset_by_prop_value(blob, off,
  325. "device_type", "cpu", 4);
  326. }
  327. if (l3_off > 0) {
  328. l3_off = fdt_node_offset_by_phandle(blob, l3_off);
  329. if (l3_off < 0) {
  330. printf("%s: %s\n", __func__, fdt_strerror(off));
  331. return ;
  332. }
  333. ft_fixup_l3cache(blob, l3_off);
  334. }
  335. }
  336. #else
  337. #define ft_fixup_l2cache(x)
  338. #endif
  339. static inline void ft_fixup_cache(void *blob)
  340. {
  341. int off;
  342. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  343. while (off != -FDT_ERR_NOTFOUND) {
  344. u32 l1cfg0 = mfspr(SPRN_L1CFG0);
  345. u32 l1cfg1 = mfspr(SPRN_L1CFG1);
  346. u32 isize, iline_size, inum_sets, inum_ways;
  347. u32 dsize, dline_size, dnum_sets, dnum_ways;
  348. /* d-side config */
  349. dsize = (l1cfg0 & 0x7ff) * 1024;
  350. dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
  351. dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
  352. dnum_sets = dsize / (dline_size * dnum_ways);
  353. fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
  354. fdt_setprop_cell(blob, off, "d-cache-size", dsize);
  355. fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
  356. #ifdef CONFIG_SYS_CACHE_STASHING
  357. {
  358. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  359. if (reg)
  360. fdt_setprop_cell(blob, off, "cache-stash-id",
  361. (*reg * 2) + 32 + 0);
  362. }
  363. #endif
  364. /* i-side config */
  365. isize = (l1cfg1 & 0x7ff) * 1024;
  366. inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
  367. iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
  368. inum_sets = isize / (iline_size * inum_ways);
  369. fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
  370. fdt_setprop_cell(blob, off, "i-cache-size", isize);
  371. fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
  372. off = fdt_node_offset_by_prop_value(blob, off,
  373. "device_type", "cpu", 4);
  374. }
  375. ft_fixup_l2cache(blob);
  376. }
  377. void fdt_add_enet_stashing(void *fdt)
  378. {
  379. do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
  380. do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
  381. do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
  382. do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
  383. do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
  384. do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
  385. }
  386. #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
  387. #ifdef CONFIG_SYS_DPAA_FMAN
  388. static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
  389. unsigned long freq)
  390. {
  391. phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
  392. int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
  393. if (off >= 0) {
  394. off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
  395. if (off > 0)
  396. printf("WARNING enable to set clock-frequency "
  397. "for %s: %s\n", compat, fdt_strerror(off));
  398. }
  399. }
  400. #endif
  401. static void ft_fixup_dpaa_clks(void *blob)
  402. {
  403. sys_info_t sysinfo;
  404. get_sys_info(&sysinfo);
  405. #ifdef CONFIG_SYS_DPAA_FMAN
  406. ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
  407. sysinfo.freq_fman[0]);
  408. #if (CONFIG_SYS_NUM_FMAN == 2)
  409. ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
  410. sysinfo.freq_fman[1]);
  411. #endif
  412. #endif
  413. #ifdef CONFIG_SYS_DPAA_QBMAN
  414. do_fixup_by_compat_u32(blob, "fsl,qman",
  415. "clock-frequency", sysinfo.freq_qman, 1);
  416. #endif
  417. #ifdef CONFIG_SYS_DPAA_PME
  418. do_fixup_by_compat_u32(blob, "fsl,pme",
  419. "clock-frequency", sysinfo.freq_pme, 1);
  420. #endif
  421. }
  422. #else
  423. #define ft_fixup_dpaa_clks(x)
  424. #endif
  425. #ifdef CONFIG_QE
  426. static void ft_fixup_qe_snum(void *blob)
  427. {
  428. unsigned int svr;
  429. svr = mfspr(SPRN_SVR);
  430. if (SVR_SOC_VER(svr) == SVR_8569) {
  431. if(IS_SVR_REV(svr, 1, 0))
  432. do_fixup_by_compat_u32(blob, "fsl,qe",
  433. "fsl,qe-num-snums", 46, 1);
  434. else
  435. do_fixup_by_compat_u32(blob, "fsl,qe",
  436. "fsl,qe-num-snums", 76, 1);
  437. }
  438. }
  439. #endif
  440. #if defined(CONFIG_ARCH_P4080)
  441. static void fdt_fixup_usb(void *fdt)
  442. {
  443. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  444. u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  445. int off;
  446. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
  447. if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
  448. FSL_CORENET_RCWSR11_EC1_FM1_USB1)
  449. fdt_status_disabled(fdt, off);
  450. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
  451. if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
  452. FSL_CORENET_RCWSR11_EC2_USB2)
  453. fdt_status_disabled(fdt, off);
  454. }
  455. #else
  456. #define fdt_fixup_usb(x)
  457. #endif
  458. #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
  459. defined(CONFIG_ARCH_T4160)
  460. void fdt_fixup_dma3(void *blob)
  461. {
  462. /* the 3rd DMA is not functional if SRIO2 is chosen */
  463. int nodeoff;
  464. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  465. #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
  466. #if defined(CONFIG_ARCH_T2080)
  467. u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  468. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  469. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  470. switch (srds_prtcl_s2) {
  471. case 0x29:
  472. case 0x2d:
  473. case 0x2e:
  474. #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
  475. u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
  476. FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
  477. srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
  478. switch (srds_prtcl_s4) {
  479. case 6:
  480. case 8:
  481. case 14:
  482. case 16:
  483. #endif
  484. nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
  485. CONFIG_SYS_ELO3_DMA3);
  486. if (nodeoff > 0)
  487. fdt_status_disabled(blob, nodeoff);
  488. else
  489. printf("WARNING: unable to disable dma3\n");
  490. break;
  491. default:
  492. break;
  493. }
  494. }
  495. #else
  496. #define fdt_fixup_dma3(x)
  497. #endif
  498. #if defined(CONFIG_ARCH_T1040)
  499. static void fdt_fixup_l2_switch(void *blob)
  500. {
  501. uchar l2swaddr[6];
  502. int node;
  503. /* The l2switch node from device-tree has
  504. * compatible string "vitesse-9953" */
  505. node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
  506. if (node == -FDT_ERR_NOTFOUND)
  507. /* no l2switch node has been found */
  508. return;
  509. /* Get MAC address for the l2switch from "l2switchaddr"*/
  510. if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
  511. printf("Warning: MAC address for l2switch not found\n");
  512. memset(l2swaddr, 0, sizeof(l2swaddr));
  513. }
  514. /* Add MAC address to l2switch node */
  515. fdt_setprop(blob, node, "local-mac-address", l2swaddr,
  516. sizeof(l2swaddr));
  517. }
  518. #else
  519. #define fdt_fixup_l2_switch(x)
  520. #endif
  521. void ft_cpu_setup(void *blob, struct bd_info *bd)
  522. {
  523. int off;
  524. int val;
  525. int len;
  526. sys_info_t sysinfo;
  527. /* delete crypto node if not on an E-processor */
  528. if (!IS_E_PROCESSOR(get_svr()))
  529. fdt_fixup_crypto_node(blob, 0);
  530. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  531. else {
  532. ccsr_sec_t __iomem *sec;
  533. sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
  534. fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
  535. }
  536. #endif
  537. fdt_add_enet_stashing(blob);
  538. #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
  539. #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
  540. #endif
  541. do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
  542. "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
  543. 1);
  544. do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
  545. "bus-frequency", bd->bi_busfreq, 1);
  546. get_sys_info(&sysinfo);
  547. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  548. while (off != -FDT_ERR_NOTFOUND) {
  549. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
  550. val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
  551. fdt_setprop(blob, off, "clock-frequency", &val, 4);
  552. off = fdt_node_offset_by_prop_value(blob, off, "device_type",
  553. "cpu", 4);
  554. }
  555. do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
  556. "bus-frequency", bd->bi_busfreq, 1);
  557. #ifdef CONFIG_QE
  558. ft_qe_setup(blob);
  559. ft_fixup_qe_snum(blob);
  560. #endif
  561. #ifdef CONFIG_SYS_DPAA_FMAN
  562. fdt_fixup_fman_firmware(blob);
  563. #endif
  564. #ifdef CONFIG_SYS_NS16550
  565. do_fixup_by_compat_u32(blob, "ns16550",
  566. "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
  567. #endif
  568. #ifdef CONFIG_CPM2
  569. do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
  570. "current-speed", gd->baudrate, 1);
  571. do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
  572. "clock-frequency", bd->bi_brgfreq, 1);
  573. #endif
  574. #ifdef CONFIG_FSL_CORENET
  575. do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
  576. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  577. do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
  578. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  579. do_fixup_by_compat_u32(blob, "fsl,mpic",
  580. "clock-frequency", get_bus_freq(0)/2, 1);
  581. #else
  582. do_fixup_by_compat_u32(blob, "fsl,mpic",
  583. "clock-frequency", get_bus_freq(0), 1);
  584. #endif
  585. fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
  586. #ifdef CONFIG_MP
  587. ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
  588. ft_fixup_num_cores(blob);
  589. #endif
  590. ft_fixup_cache(blob);
  591. #if defined(CONFIG_FSL_ESDHC)
  592. fdt_fixup_esdhc(blob, bd);
  593. #endif
  594. ft_fixup_dpaa_clks(blob);
  595. #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
  596. fdt_portal(blob, "fsl,bman-portal", "bman-portals",
  597. (u64)CONFIG_SYS_BMAN_MEM_PHYS,
  598. CONFIG_SYS_BMAN_MEM_SIZE);
  599. fdt_fixup_bportals(blob);
  600. #endif
  601. #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
  602. fdt_portal(blob, "fsl,qman-portal", "qman-portals",
  603. (u64)CONFIG_SYS_QMAN_MEM_PHYS,
  604. CONFIG_SYS_QMAN_MEM_SIZE);
  605. fdt_fixup_qportals(blob);
  606. #endif
  607. #ifdef CONFIG_SYS_SRIO
  608. ft_srio_setup(blob);
  609. #endif
  610. /*
  611. * system-clock = CCB clock/2
  612. * Here gd->bus_clk = CCB clock
  613. * We are using the system clock as 1588 Timer reference
  614. * clock source select
  615. */
  616. do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
  617. "timer-frequency", gd->bus_clk/2, 1);
  618. /*
  619. * clock-freq should change to clock-frequency and
  620. * flexcan-v1.0 should change to p1010-flexcan respectively
  621. * in the future.
  622. */
  623. do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
  624. "clock_freq", gd->bus_clk/2, 1);
  625. do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
  626. "clock-frequency", gd->bus_clk/2, 1);
  627. do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
  628. "clock-frequency", gd->bus_clk/2, 1);
  629. fdt_fixup_usb(blob);
  630. fdt_fixup_l2_switch(blob);
  631. fdt_fixup_dma3(blob);
  632. }
  633. /*
  634. * For some CCSR devices, we only have the virtual address, not the physical
  635. * address. This is because we map CCSR as a whole, so we typically don't need
  636. * a macro for the physical address of any device within CCSR. In this case,
  637. * we calculate the physical address of that device using it's the difference
  638. * between the virtual address of the device and the virtual address of the
  639. * beginning of CCSR.
  640. */
  641. #define CCSR_VIRT_TO_PHYS(x) \
  642. (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
  643. static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
  644. {
  645. printf("Warning: U-Boot configured %s at address %llx,\n"
  646. "but the device tree has it at %llx\n", name, uaddr, daddr);
  647. }
  648. /*
  649. * Verify the device tree
  650. *
  651. * This function compares several CONFIG_xxx macros that contain physical
  652. * addresses with the corresponding nodes in the device tree, to see if
  653. * the physical addresses are all correct. For example, if
  654. * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
  655. * of the first UART. We convert this to a physical address and compare
  656. * that with the physical address of the first ns16550-compatible node
  657. * in the device tree. If they don't match, then we display a warning.
  658. *
  659. * Returns 1 on success, 0 on failure
  660. */
  661. int ft_verify_fdt(void *fdt)
  662. {
  663. uint64_t addr = 0;
  664. int aliases;
  665. int off;
  666. /* First check the CCSR base address */
  667. off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
  668. if (off > 0) {
  669. int size;
  670. u32 naddr;
  671. const fdt32_t *prop;
  672. naddr = fdt_address_cells(fdt, off);
  673. prop = fdt_getprop(fdt, off, "ranges", &size);
  674. addr = fdt_translate_address(fdt, off, prop + naddr);
  675. }
  676. if (!addr) {
  677. printf("Warning: could not determine base CCSR address in "
  678. "device tree\n");
  679. /* No point in checking anything else */
  680. return 0;
  681. }
  682. if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
  683. msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
  684. /* No point in checking anything else */
  685. return 0;
  686. }
  687. /*
  688. * Check some nodes via aliases. We assume that U-Boot and the device
  689. * tree enumerate the devices equally. E.g. the first serial port in
  690. * U-Boot is the same as "serial0" in the device tree.
  691. */
  692. aliases = fdt_path_offset(fdt, "/aliases");
  693. if (aliases > 0) {
  694. #ifdef CONFIG_SYS_NS16550_COM1
  695. if (!fdt_verify_alias_address(fdt, aliases, "serial0",
  696. CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
  697. return 0;
  698. #endif
  699. #ifdef CONFIG_SYS_NS16550_COM2
  700. if (!fdt_verify_alias_address(fdt, aliases, "serial1",
  701. CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
  702. return 0;
  703. #endif
  704. }
  705. /*
  706. * The localbus node is typically a root node, even though the lbc
  707. * controller is part of CCSR. If we were to put the lbc node under
  708. * the SOC node, then the 'ranges' property in the lbc node would
  709. * translate through the 'ranges' property of the parent SOC node, and
  710. * we don't want that. Since it's a separate node, it's possible for
  711. * the 'reg' property to be wrong, so check it here. For now, we
  712. * only check for "fsl,elbc" nodes.
  713. */
  714. #ifdef CONFIG_SYS_LBC_ADDR
  715. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
  716. if (off > 0) {
  717. const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
  718. if (reg) {
  719. uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
  720. addr = fdt_translate_address(fdt, off, reg);
  721. if (uaddr != addr) {
  722. msg("the localbus", uaddr, addr);
  723. return 0;
  724. }
  725. }
  726. }
  727. #endif
  728. return 1;
  729. }
  730. void fdt_del_diu(void *blob)
  731. {
  732. int nodeoff = 0;
  733. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  734. "fsl,diu")) >= 0) {
  735. fdt_del_node(blob, nodeoff);
  736. }
  737. }