ether_fcc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * MPC8560 FCC Fast Ethernet
  4. * Copyright (c) 2003 Motorola,Inc.
  5. * Xianghua Xiao, (X.Xiao@motorola.com)
  6. *
  7. * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
  8. *
  9. * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  10. * Marius Groeger <mgroeger@sysgo.de>
  11. */
  12. /*
  13. * MPC8560 FCC Fast Ethernet
  14. * Basic ET HW initialization and packet RX/TX routines
  15. *
  16. * This code will not perform the IO port configuration. This should be
  17. * done in the iop_conf_t structure specific for the board.
  18. *
  19. * TODO:
  20. * add a PHY driver to do the negotiation
  21. * reflect negotiation results in FPSMR
  22. * look for ways to configure the board specific stuff elsewhere, eg.
  23. * config_xxx.h or the board directory
  24. */
  25. #include <common.h>
  26. #include <malloc.h>
  27. #include <asm/cpm_85xx.h>
  28. #include <command.h>
  29. #include <config.h>
  30. #include <net.h>
  31. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  32. #include <miiphy.h>
  33. #endif
  34. #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET)
  35. static struct ether_fcc_info_s
  36. {
  37. int ether_index;
  38. int proff_enet;
  39. ulong cpm_cr_enet_sblock;
  40. ulong cpm_cr_enet_page;
  41. ulong cmxfcr_mask;
  42. ulong cmxfcr_value;
  43. }
  44. ether_fcc_info[] =
  45. {
  46. #ifdef CONFIG_ETHER_ON_FCC1
  47. {
  48. 0,
  49. PROFF_FCC1,
  50. CPM_CR_FCC1_SBLOCK,
  51. CPM_CR_FCC1_PAGE,
  52. CONFIG_SYS_CMXFCR_MASK1,
  53. CONFIG_SYS_CMXFCR_VALUE1
  54. },
  55. #endif
  56. #ifdef CONFIG_ETHER_ON_FCC2
  57. {
  58. 1,
  59. PROFF_FCC2,
  60. CPM_CR_FCC2_SBLOCK,
  61. CPM_CR_FCC2_PAGE,
  62. CONFIG_SYS_CMXFCR_MASK2,
  63. CONFIG_SYS_CMXFCR_VALUE2
  64. },
  65. #endif
  66. #ifdef CONFIG_ETHER_ON_FCC3
  67. {
  68. 2,
  69. PROFF_FCC3,
  70. CPM_CR_FCC3_SBLOCK,
  71. CPM_CR_FCC3_PAGE,
  72. CONFIG_SYS_CMXFCR_MASK3,
  73. CONFIG_SYS_CMXFCR_VALUE3
  74. },
  75. #endif
  76. };
  77. /*---------------------------------------------------------------------*/
  78. /* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
  79. #define PKT_MAXDMA_SIZE 1520
  80. /* The FCC stores dest/src/type, data, and checksum for receive packets. */
  81. #define PKT_MAXBUF_SIZE 1518
  82. #define PKT_MINBUF_SIZE 64
  83. /* Maximum input buffer size. Must be a multiple of 32. */
  84. #define PKT_MAXBLR_SIZE 1536
  85. #define TOUT_LOOP 1000000
  86. #define TX_BUF_CNT 2
  87. static uint rxIdx; /* index of the current RX buffer */
  88. static uint txIdx; /* index of the current TX buffer */
  89. /*
  90. * FCC Ethernet Tx and Rx buffer descriptors.
  91. * Provide for Double Buffering
  92. * Note: PKTBUFSRX is defined in net.h
  93. */
  94. typedef volatile struct rtxbd {
  95. cbd_t rxbd[PKTBUFSRX];
  96. cbd_t txbd[TX_BUF_CNT];
  97. } RTXBD;
  98. /* Good news: the FCC supports external BDs! */
  99. #ifdef __GNUC__
  100. static RTXBD rtx __attribute__ ((aligned(8)));
  101. #else
  102. #error "rtx must be 64-bit aligned"
  103. #endif
  104. #undef ET_DEBUG
  105. static int fec_send(struct eth_device *dev, void *packet, int length)
  106. {
  107. int i = 0;
  108. int result = 0;
  109. if (length <= 0) {
  110. printf("fec: bad packet size: %d\n", length);
  111. goto out;
  112. }
  113. for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
  114. if (i >= TOUT_LOOP) {
  115. printf("fec: tx buffer not ready\n");
  116. goto out;
  117. }
  118. }
  119. rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
  120. rtx.txbd[txIdx].cbd_datlen = length;
  121. rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
  122. BD_ENET_TX_TC | BD_ENET_TX_PAD);
  123. for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
  124. if (i >= TOUT_LOOP) {
  125. printf("fec: tx error\n");
  126. goto out;
  127. }
  128. }
  129. #ifdef ET_DEBUG
  130. printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
  131. printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
  132. for(i=0;i<(length/16 + 1);i++) {
  133. printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
  134. *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
  135. *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
  136. }
  137. #endif
  138. /* return only status bits */
  139. result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
  140. txIdx = (txIdx + 1) % TX_BUF_CNT;
  141. out:
  142. return result;
  143. }
  144. static int fec_recv(struct eth_device* dev)
  145. {
  146. int length;
  147. for (;;)
  148. {
  149. if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
  150. length = -1;
  151. break; /* nothing received - leave for() loop */
  152. }
  153. length = rtx.rxbd[rxIdx].cbd_datlen;
  154. if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
  155. printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
  156. }
  157. else {
  158. /* Pass the packet up to the protocol layers. */
  159. net_process_received_packet(net_rx_packets[rxIdx], length - 4);
  160. }
  161. /* Give the buffer back to the FCC. */
  162. rtx.rxbd[rxIdx].cbd_datlen = 0;
  163. /* wrap around buffer index when necessary */
  164. if ((rxIdx + 1) >= PKTBUFSRX) {
  165. rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  166. rxIdx = 0;
  167. }
  168. else {
  169. rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
  170. rxIdx++;
  171. }
  172. }
  173. return length;
  174. }
  175. static int fec_init(struct eth_device* dev, struct bd_info *bis)
  176. {
  177. struct ether_fcc_info_s * info = dev->priv;
  178. int i;
  179. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  180. volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
  181. fcc_enet_t *pram_ptr;
  182. unsigned long mem_addr;
  183. #if 0
  184. mii_discover_phy();
  185. #endif
  186. /* 28.9 - (1-2): ioports have been set up already */
  187. /* 28.9 - (3): connect FCC's tx and rx clocks */
  188. cpm->im_cpm_mux.cmxuar = 0; /* ATM */
  189. cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
  190. info->cmxfcr_value;
  191. /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
  192. if(info->ether_index == 0) {
  193. cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
  194. } else if (info->ether_index == 1) {
  195. cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
  196. } else if (info->ether_index == 2) {
  197. cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
  198. }
  199. /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
  200. if(info->ether_index == 0) {
  201. cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
  202. } else if (info->ether_index == 1){
  203. cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
  204. } else if (info->ether_index == 2){
  205. cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
  206. }
  207. /* 28.9 - (6): FDSR: Ethernet Syn */
  208. if(info->ether_index == 0) {
  209. cpm->im_cpm_fcc1.fdsr = 0xD555;
  210. } else if (info->ether_index == 1) {
  211. cpm->im_cpm_fcc2.fdsr = 0xD555;
  212. } else if (info->ether_index == 2) {
  213. cpm->im_cpm_fcc3.fdsr = 0xD555;
  214. }
  215. /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
  216. rxIdx = 0;
  217. txIdx = 0;
  218. /* Setup Receiver Buffer Descriptors */
  219. for (i = 0; i < PKTBUFSRX; i++)
  220. {
  221. rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  222. rtx.rxbd[i].cbd_datlen = 0;
  223. rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
  224. }
  225. rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  226. /* Setup Ethernet Transmitter Buffer Descriptors */
  227. for (i = 0; i < TX_BUF_CNT; i++)
  228. {
  229. rtx.txbd[i].cbd_sc = 0;
  230. rtx.txbd[i].cbd_datlen = 0;
  231. rtx.txbd[i].cbd_bufaddr = 0;
  232. }
  233. rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
  234. /* 28.9 - (7): initialize parameter ram */
  235. pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
  236. /* clear whole structure to make sure all reserved fields are zero */
  237. memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
  238. /*
  239. * common Parameter RAM area
  240. *
  241. * Allocate space in the reserved FCC area of DPRAM for the
  242. * internal buffers. No one uses this space (yet), so we
  243. * can do this. Later, we will add resource management for
  244. * this area.
  245. * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560
  246. * 0x9000 for MPC8541, MPC8555
  247. */
  248. mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
  249. pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
  250. pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
  251. /*
  252. * Set maximum bytes per receive buffer.
  253. * It must be a multiple of 32.
  254. */
  255. pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
  256. /* localbus SDRAM should be preferred */
  257. pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
  258. CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
  259. pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
  260. pram_ptr->fen_genfcc.fcc_rbdstat = 0;
  261. pram_ptr->fen_genfcc.fcc_rbdlen = 0;
  262. pram_ptr->fen_genfcc.fcc_rdptr = 0;
  263. /* localbus SDRAM should be preferred */
  264. pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
  265. CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
  266. pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
  267. pram_ptr->fen_genfcc.fcc_tbdstat = 0;
  268. pram_ptr->fen_genfcc.fcc_tbdlen = 0;
  269. pram_ptr->fen_genfcc.fcc_tdptr = 0;
  270. /* protocol-specific area */
  271. pram_ptr->fen_statbuf = 0x0;
  272. pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
  273. pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
  274. pram_ptr->fen_crcec = 0;
  275. pram_ptr->fen_alec = 0;
  276. pram_ptr->fen_disfc = 0;
  277. pram_ptr->fen_retlim = 15; /* Retry limit threshold */
  278. pram_ptr->fen_retcnt = 0;
  279. pram_ptr->fen_pper = 0;
  280. pram_ptr->fen_boffcnt = 0;
  281. pram_ptr->fen_gaddrh = 0;
  282. pram_ptr->fen_gaddrl = 0;
  283. pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
  284. /*
  285. * Set Ethernet station address.
  286. *
  287. * This is supplied in the board information structure, so we
  288. * copy that into the controller.
  289. * So far we have only been given one Ethernet address. We make
  290. * it unique by setting a few bits in the upper byte of the
  291. * non-static part of the address.
  292. */
  293. #define ea eth_get_ethaddr()
  294. pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
  295. pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
  296. pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
  297. #undef ea
  298. pram_ptr->fen_ibdcount = 0;
  299. pram_ptr->fen_ibdstart = 0;
  300. pram_ptr->fen_ibdend = 0;
  301. pram_ptr->fen_txlen = 0;
  302. pram_ptr->fen_iaddrh = 0; /* disable hash */
  303. pram_ptr->fen_iaddrl = 0;
  304. pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
  305. /* pad pointer. use tiptr since we don't need a specific padding char */
  306. pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
  307. pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */
  308. pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */
  309. #if defined(ET_DEBUG)
  310. printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
  311. printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
  312. pram_ptr->fen_genfcc.fcc_rbase);
  313. printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
  314. pram_ptr->fen_genfcc.fcc_tbase);
  315. #endif
  316. /* 28.9 - (8)(9): clear out events in FCCE */
  317. /* 28.9 - (9): FCCM: mask all events */
  318. if(info->ether_index == 0) {
  319. cpm->im_cpm_fcc1.fcce = ~0x0;
  320. cpm->im_cpm_fcc1.fccm = 0;
  321. } else if (info->ether_index == 1) {
  322. cpm->im_cpm_fcc2.fcce = ~0x0;
  323. cpm->im_cpm_fcc2.fccm = 0;
  324. } else if (info->ether_index == 2) {
  325. cpm->im_cpm_fcc3.fcce = ~0x0;
  326. cpm->im_cpm_fcc3.fccm = 0;
  327. }
  328. /* 28.9 - (10-12): we don't use ethernet interrupts */
  329. /* 28.9 - (13)
  330. *
  331. * Let's re-initialize the channel now. We have to do it later
  332. * than the manual describes because we have just now finished
  333. * the BD initialization.
  334. */
  335. cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
  336. info->cpm_cr_enet_sblock,
  337. 0x0c,
  338. CPM_CR_INIT_TRX) | CPM_CR_FLG;
  339. do {
  340. __asm__ __volatile__ ("eieio");
  341. } while (cp->cpcr & CPM_CR_FLG);
  342. /* 28.9 - (14): enable tx/rx in gfmr */
  343. if(info->ether_index == 0) {
  344. cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
  345. } else if (info->ether_index == 1) {
  346. cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
  347. } else if (info->ether_index == 2) {
  348. cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
  349. }
  350. return 1;
  351. }
  352. static void fec_halt(struct eth_device* dev)
  353. {
  354. struct ether_fcc_info_s * info = dev->priv;
  355. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  356. /* write GFMR: disable tx/rx */
  357. if(info->ether_index == 0) {
  358. cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
  359. } else if(info->ether_index == 1) {
  360. cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
  361. } else if(info->ether_index == 2) {
  362. cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
  363. }
  364. }
  365. int fec_initialize(struct bd_info *bis)
  366. {
  367. struct eth_device* dev;
  368. int i;
  369. for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
  370. {
  371. dev = (struct eth_device*) malloc(sizeof *dev);
  372. memset(dev, 0, sizeof *dev);
  373. sprintf(dev->name, "FCC%d",
  374. ether_fcc_info[i].ether_index + 1);
  375. dev->priv = &ether_fcc_info[i];
  376. dev->init = fec_init;
  377. dev->halt = fec_halt;
  378. dev->send = fec_send;
  379. dev->recv = fec_recv;
  380. eth_register(dev);
  381. #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
  382. && defined(CONFIG_BITBANGMII)
  383. int retval;
  384. struct mii_dev *mdiodev = mdio_alloc();
  385. if (!mdiodev)
  386. return -ENOMEM;
  387. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  388. mdiodev->read = bb_miiphy_read;
  389. mdiodev->write = bb_miiphy_write;
  390. retval = mdio_register(mdiodev);
  391. if (retval < 0)
  392. return retval;
  393. #endif
  394. }
  395. return 1;
  396. }
  397. #endif