cpu_init_early.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc
  4. */
  5. #include <common.h>
  6. #include <asm-offsets.h>
  7. #include <asm/processor.h>
  8. #include <asm/mmu.h>
  9. #include <asm/fsl_law.h>
  10. #include <asm/io.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. #ifdef CONFIG_A003399_NOR_WORKAROUND
  13. void setup_ifc(void)
  14. {
  15. struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  16. u32 _mas0, _mas1, _mas2, _mas3, _mas7;
  17. phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
  18. /*
  19. * Adjust the TLB we were running out of to match the phys addr of the
  20. * chip select we are adjusting and will return to.
  21. */
  22. flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
  23. _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
  24. _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
  25. MAS1_TSIZE(BOOKE_PAGESZ_4M);
  26. _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
  27. _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
  28. _mas7 = FSL_BOOKE_MAS7(flash_phys);
  29. mtspr(MAS0, _mas0);
  30. mtspr(MAS1, _mas1);
  31. mtspr(MAS2, _mas2);
  32. mtspr(MAS3, _mas3);
  33. mtspr(MAS7, _mas7);
  34. asm volatile("isync;msync;tlbwe;isync");
  35. #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
  36. /*
  37. * TLB entry for debuggging in AS1
  38. * Create temporary TLB entry in AS0 to handle debug exception
  39. * As on debug exception MSR is cleared i.e. Address space is changed
  40. * to 0. A TLB entry (in AS0) is required to handle debug exception generated
  41. * in AS1.
  42. *
  43. * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  44. * bacause flash's physical address is going to change as
  45. * CONFIG_SYS_FLASH_BASE_PHYS.
  46. */
  47. _mas0 = MAS0_TLBSEL(1) |
  48. MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
  49. _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
  50. MAS1_TSIZE(BOOKE_PAGESZ_4M);
  51. _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
  52. _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
  53. _mas7 = FSL_BOOKE_MAS7(flash_phys);
  54. mtspr(MAS0, _mas0);
  55. mtspr(MAS1, _mas1);
  56. mtspr(MAS2, _mas2);
  57. mtspr(MAS3, _mas3);
  58. mtspr(MAS7, _mas7);
  59. asm volatile("isync;msync;tlbwe;isync");
  60. #endif
  61. /* Change flash's physical address */
  62. ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
  63. ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
  64. ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
  65. return ;
  66. }
  67. #endif
  68. /* We run cpu_init_early_f in AS = 1 */
  69. void cpu_init_early_f(void *fdt)
  70. {
  71. u32 mas0, mas1, mas2, mas3, mas7;
  72. #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  73. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  74. #endif
  75. #ifdef CONFIG_A003399_NOR_WORKAROUND
  76. ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  77. u32 *dst, *src;
  78. void (*setup_ifc_sram)(void);
  79. int i;
  80. #endif
  81. /* Pointer is writable since we allocated a register for it */
  82. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  83. /* gd area was zeroed during startup */
  84. #ifdef CONFIG_ARCH_QEMU_E500
  85. /*
  86. * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
  87. * so we need to populate it before it accesses it.
  88. */
  89. gd->fdt_blob = fdt;
  90. #endif
  91. mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
  92. mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
  93. mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
  94. mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
  95. mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
  96. write_tlb(mas0, mas1, mas2, mas3, mas7);
  97. /*
  98. * Work Around for IFC Erratum A-003549. This issue is P1010
  99. * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
  100. * Hence specifically selecting CS3.
  101. */
  102. #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  103. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
  104. #endif
  105. init_laws();
  106. /*
  107. * Work Around for IFC Erratum A003399, issue will hit only when execution
  108. * from NOR Flash
  109. */
  110. #ifdef CONFIG_A003399_NOR_WORKAROUND
  111. #define SRAM_BASE_ADDR (0x00000000)
  112. /* TLB for SRAM */
  113. mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
  114. mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
  115. MAS1_TSIZE(BOOKE_PAGESZ_1M);
  116. mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
  117. mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
  118. mas7 = FSL_BOOKE_MAS7(0);
  119. write_tlb(mas0, mas1, mas2, mas3, mas7);
  120. out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
  121. out_be32(&l2cache->l2errdis,
  122. (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
  123. out_be32(&l2cache->l2ctl,
  124. (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
  125. /*
  126. * Copy the code in setup_ifc to L2SRAM. Do a word copy
  127. * because NOR Flash on P1010 does not support byte
  128. * access (Erratum IFC-A002769)
  129. */
  130. setup_ifc_sram = (void *)SRAM_BASE_ADDR;
  131. dst = (u32 *) SRAM_BASE_ADDR;
  132. src = (u32 *) setup_ifc;
  133. for (i = 0; i < 1024; i++) {
  134. /* cppcheck-suppress nullPointer */
  135. *dst++ = *src++;
  136. }
  137. /* cppcheck-suppress nullPointer */
  138. setup_ifc_sram();
  139. /* CLEANUP */
  140. clrbits_be32(&l2cache->l2ctl,
  141. (MPC85xx_L2CTL_L2E |
  142. MPC85xx_L2CTL_L2SRAM_ENTIRE));
  143. out_be32(&l2cache->l2srbar0, 0x0);
  144. #endif
  145. invalidate_tlb(1);
  146. #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
  147. !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
  148. !defined(CONFIG_NAND_SPL)
  149. disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
  150. #endif
  151. init_tlbs();
  152. }