cpu.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
  4. * (C) Copyright 2002, 2003 Motorola Inc.
  5. * Xianghua Xiao (X.Xiao@motorola.com)
  6. *
  7. * (C) Copyright 2000
  8. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  9. */
  10. #include <config.h>
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <init.h>
  14. #include <irq_func.h>
  15. #include <log.h>
  16. #include <time.h>
  17. #include <vsprintf.h>
  18. #include <watchdog.h>
  19. #include <command.h>
  20. #include <fsl_esdhc.h>
  21. #include <asm/cache.h>
  22. #include <asm/io.h>
  23. #include <asm/mmu.h>
  24. #include <fsl_ifc.h>
  25. #include <asm/fsl_law.h>
  26. #include <asm/fsl_lbc.h>
  27. #include <post.h>
  28. #include <asm/processor.h>
  29. #include <fsl_ddr_sdram.h>
  30. #include <asm/ppc.h>
  31. #include <linux/delay.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. /*
  34. * Default board reset function
  35. */
  36. static void
  37. __board_reset(void)
  38. {
  39. /* Do nothing */
  40. }
  41. void board_reset(void) __attribute__((weak, alias("__board_reset")));
  42. int checkcpu (void)
  43. {
  44. sys_info_t sysinfo;
  45. uint pvr, svr;
  46. uint ver;
  47. uint major, minor;
  48. struct cpu_type *cpu;
  49. char buf1[32], buf2[32];
  50. #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
  51. ccsr_gur_t __iomem *gur =
  52. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  53. #endif
  54. /*
  55. * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
  56. * mode. Previous platform use ddr ratio to do the same. This
  57. * information is only for display here.
  58. */
  59. #ifdef CONFIG_FSL_CORENET
  60. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  61. u32 ddr_sync = 0; /* only async mode is supported */
  62. #else
  63. u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
  64. >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
  65. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  66. #else /* CONFIG_FSL_CORENET */
  67. #ifdef CONFIG_DDR_CLK_FREQ
  68. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  69. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  70. #else
  71. u32 ddr_ratio = 0;
  72. #endif /* CONFIG_DDR_CLK_FREQ */
  73. #endif /* CONFIG_FSL_CORENET */
  74. unsigned int i, core, nr_cores = cpu_numcores();
  75. u32 mask = cpu_mask();
  76. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  77. unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
  78. u32 dsp_mask = cpu_dsp_mask();
  79. #endif
  80. svr = get_svr();
  81. major = SVR_MAJ(svr);
  82. minor = SVR_MIN(svr);
  83. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  84. if (SVR_SOC_VER(svr) == SVR_T4080) {
  85. ccsr_rcpm_t *rcpm =
  86. (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  87. setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
  88. FSL_CORENET_DEVDISR2_DTSEC1_9);
  89. setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
  90. setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
  91. /* It needs SW to disable core4~7 as HW design sake on T4080 */
  92. for (i = 4; i < 8; i++)
  93. cpu_disable(i);
  94. /* request core4~7 into PH20 state, prior to entering PCL10
  95. * state, all cores in cluster should be placed in PH20 state.
  96. */
  97. setbits_be32(&rcpm->pcph20setr, 0xf0);
  98. /* put the 2nd cluster into PCL10 state */
  99. setbits_be32(&rcpm->clpcl10setr, 1 << 1);
  100. }
  101. #endif
  102. if (cpu_numcores() > 1) {
  103. #ifndef CONFIG_MP
  104. puts("Unicore software on multiprocessor system!!\n"
  105. "To enable mutlticore build define CONFIG_MP\n");
  106. #endif
  107. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  108. printf("CPU%d: ", pic->whoami);
  109. } else {
  110. puts("CPU: ");
  111. }
  112. cpu = gd->arch.cpu;
  113. puts(cpu->name);
  114. if (IS_E_PROCESSOR(svr))
  115. puts("E");
  116. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  117. pvr = get_pvr();
  118. ver = PVR_VER(pvr);
  119. major = PVR_MAJ(pvr);
  120. minor = PVR_MIN(pvr);
  121. printf("Core: ");
  122. switch(ver) {
  123. case PVR_VER_E500_V1:
  124. case PVR_VER_E500_V2:
  125. puts("e500");
  126. break;
  127. case PVR_VER_E500MC:
  128. puts("e500mc");
  129. break;
  130. case PVR_VER_E5500:
  131. puts("e5500");
  132. break;
  133. case PVR_VER_E6500:
  134. puts("e6500");
  135. break;
  136. default:
  137. puts("Unknown");
  138. break;
  139. }
  140. printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  141. if (nr_cores > CONFIG_MAX_CPUS) {
  142. panic("\nUnexpected number of cores: %d, max is %d\n",
  143. nr_cores, CONFIG_MAX_CPUS);
  144. }
  145. get_sys_info(&sysinfo);
  146. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  147. if (sysinfo.diff_sysclk == 1)
  148. puts("Single Source Clock Configuration\n");
  149. #endif
  150. puts("Clock Configuration:");
  151. for_each_cpu(i, core, nr_cores, mask) {
  152. if (!(i & 3))
  153. printf ("\n ");
  154. printf("CPU%d:%-4s MHz, ", core,
  155. strmhz(buf1, sysinfo.freq_processor[core]));
  156. }
  157. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  158. for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
  159. if (!(j & 3))
  160. printf("\n ");
  161. printf("DSP CPU%d:%-4s MHz, ", j,
  162. strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
  163. }
  164. #endif
  165. printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
  166. printf("\n");
  167. #ifdef CONFIG_FSL_CORENET
  168. if (ddr_sync == 1) {
  169. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  170. "(Synchronous), ",
  171. strmhz(buf1, sysinfo.freq_ddrbus/2),
  172. strmhz(buf2, sysinfo.freq_ddrbus));
  173. } else {
  174. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  175. "(Asynchronous), ",
  176. strmhz(buf1, sysinfo.freq_ddrbus/2),
  177. strmhz(buf2, sysinfo.freq_ddrbus));
  178. }
  179. #else
  180. switch (ddr_ratio) {
  181. case 0x0:
  182. printf(" DDR:%-4s MHz (%s MT/s data rate), ",
  183. strmhz(buf1, sysinfo.freq_ddrbus/2),
  184. strmhz(buf2, sysinfo.freq_ddrbus));
  185. break;
  186. case 0x7:
  187. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  188. "(Synchronous), ",
  189. strmhz(buf1, sysinfo.freq_ddrbus/2),
  190. strmhz(buf2, sysinfo.freq_ddrbus));
  191. break;
  192. default:
  193. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  194. "(Asynchronous), ",
  195. strmhz(buf1, sysinfo.freq_ddrbus/2),
  196. strmhz(buf2, sysinfo.freq_ddrbus));
  197. break;
  198. }
  199. #endif
  200. #if defined(CONFIG_FSL_LBC)
  201. if (sysinfo.freq_localbus > LCRR_CLKDIV) {
  202. printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  203. } else {
  204. printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
  205. sysinfo.freq_localbus);
  206. }
  207. #endif
  208. #if defined(CONFIG_FSL_IFC)
  209. printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  210. #endif
  211. #ifdef CONFIG_CPM2
  212. printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
  213. #endif
  214. #ifdef CONFIG_QE
  215. printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
  216. #endif
  217. #if defined(CONFIG_SYS_CPRI)
  218. printf(" ");
  219. printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
  220. #endif
  221. #if defined(CONFIG_SYS_MAPLE)
  222. printf("\n ");
  223. printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
  224. printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
  225. printf("MAPLE-eTVPE:%-4s MHz\n",
  226. strmhz(buf1, sysinfo.freq_maple_etvpe));
  227. #endif
  228. #ifdef CONFIG_SYS_DPAA_FMAN
  229. for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
  230. printf(" FMAN%d: %s MHz\n", i + 1,
  231. strmhz(buf1, sysinfo.freq_fman[i]));
  232. }
  233. #endif
  234. #ifdef CONFIG_SYS_DPAA_QBMAN
  235. printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
  236. #endif
  237. #ifdef CONFIG_SYS_DPAA_PME
  238. printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
  239. #endif
  240. puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
  241. #ifdef CONFIG_FSL_CORENET
  242. /* Display the RCW, so that no one gets confused as to what RCW
  243. * we're actually using for this boot.
  244. */
  245. puts("Reset Configuration Word (RCW):");
  246. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  247. u32 rcw = in_be32(&gur->rcwsr[i]);
  248. if ((i % 4) == 0)
  249. printf("\n %08x:", i * 4);
  250. printf(" %08x", rcw);
  251. }
  252. puts("\n");
  253. #endif
  254. return 0;
  255. }
  256. /* ------------------------------------------------------------------------- */
  257. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  258. {
  259. /* Everything after the first generation of PQ3 parts has RSTCR */
  260. #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
  261. defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
  262. unsigned long val, msr;
  263. /*
  264. * Initiate hard reset in debug control register DBCR0
  265. * Make sure MSR[DE] = 1. This only resets the core.
  266. */
  267. msr = mfmsr ();
  268. msr |= MSR_DE;
  269. mtmsr (msr);
  270. val = mfspr(DBCR0);
  271. val |= 0x70000000;
  272. mtspr(DBCR0,val);
  273. #else
  274. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  275. /* Attempt board-specific reset */
  276. board_reset();
  277. /* Next try asserting HRESET_REQ */
  278. out_be32(&gur->rstcr, 0x2);
  279. udelay(100);
  280. #endif
  281. return 1;
  282. }
  283. /*
  284. * Get timebase clock frequency
  285. */
  286. #ifndef CONFIG_SYS_FSL_TBCLK_DIV
  287. #define CONFIG_SYS_FSL_TBCLK_DIV 8
  288. #endif
  289. __weak unsigned long get_tbclk(void)
  290. {
  291. unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
  292. return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
  293. }
  294. #if defined(CONFIG_WATCHDOG)
  295. #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
  296. void
  297. init_85xx_watchdog(void)
  298. {
  299. mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
  300. TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
  301. }
  302. void
  303. reset_85xx_watchdog(void)
  304. {
  305. /*
  306. * Clear TSR(WIS) bit by writing 1
  307. */
  308. mtspr(SPRN_TSR, TSR_WIS);
  309. }
  310. void
  311. watchdog_reset(void)
  312. {
  313. int re_enable = disable_interrupts();
  314. reset_85xx_watchdog();
  315. if (re_enable)
  316. enable_interrupts();
  317. }
  318. #endif /* CONFIG_WATCHDOG */
  319. /*
  320. * Initializes on-chip MMC controllers.
  321. * to override, implement board_mmc_init()
  322. */
  323. int cpu_mmc_init(struct bd_info *bis)
  324. {
  325. #ifdef CONFIG_FSL_ESDHC
  326. return fsl_esdhc_mmc_init(bis);
  327. #else
  328. return 0;
  329. #endif
  330. }
  331. /*
  332. * Print out the state of various machine registers.
  333. * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
  334. * parameters for IFC and TLBs
  335. */
  336. void print_reginfo(void)
  337. {
  338. print_tlbcam();
  339. print_laws();
  340. #if defined(CONFIG_FSL_LBC)
  341. print_lbc_regs();
  342. #endif
  343. #ifdef CONFIG_FSL_IFC
  344. print_ifc_regs();
  345. #endif
  346. }
  347. /* Common ddr init for non-corenet fsl 85xx platforms */
  348. #ifndef CONFIG_FSL_CORENET
  349. #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
  350. !defined(CONFIG_SYS_INIT_L2_ADDR)
  351. int dram_init(void)
  352. {
  353. #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
  354. defined(CONFIG_ARCH_QEMU_E500)
  355. gd->ram_size = fsl_ddr_sdram_size();
  356. #else
  357. gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  358. #endif
  359. return 0;
  360. }
  361. #else /* CONFIG_SYS_RAMBOOT */
  362. int dram_init(void)
  363. {
  364. phys_size_t dram_size = 0;
  365. #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
  366. {
  367. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  368. unsigned int x = 10;
  369. unsigned int i;
  370. /*
  371. * Work around to stabilize DDR DLL
  372. */
  373. out_be32(&gur->ddrdllcr, 0x81000000);
  374. asm("sync;isync;msync");
  375. udelay(200);
  376. while (in_be32(&gur->ddrdllcr) != 0x81000100) {
  377. setbits_be32(&gur->devdisr, 0x00010000);
  378. for (i = 0; i < x; i++)
  379. ;
  380. clrbits_be32(&gur->devdisr, 0x00010000);
  381. x++;
  382. }
  383. }
  384. #endif
  385. #if defined(CONFIG_SPD_EEPROM) || \
  386. defined(CONFIG_DDR_SPD) || \
  387. defined(CONFIG_SYS_DDR_RAW_TIMING)
  388. dram_size = fsl_ddr_sdram();
  389. #else
  390. dram_size = fixed_sdram();
  391. #endif
  392. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  393. dram_size *= 0x100000;
  394. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  395. /*
  396. * Initialize and enable DDR ECC.
  397. */
  398. ddr_enable_ecc(dram_size);
  399. #endif
  400. #if defined(CONFIG_FSL_LBC)
  401. /* Some boards also have sdram on the lbc */
  402. lbc_sdram_init();
  403. #endif
  404. debug("DDR: ");
  405. gd->ram_size = dram_size;
  406. return 0;
  407. }
  408. #endif /* CONFIG_SYS_RAMBOOT */
  409. #endif
  410. #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
  411. /* Board-specific functions defined in each board's ddr.c */
  412. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  413. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
  414. void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
  415. phys_addr_t *rpn);
  416. unsigned int
  417. setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  418. void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  419. static void dump_spd_ddr_reg(void)
  420. {
  421. int i, j, k, m;
  422. u8 *p_8;
  423. u32 *p_32;
  424. struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
  425. generic_spd_eeprom_t
  426. spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
  427. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
  428. fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
  429. puts("SPD data of all dimms (zero value is omitted)...\n");
  430. puts("Byte (hex) ");
  431. k = 1;
  432. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  433. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
  434. printf("Dimm%d ", k++);
  435. }
  436. puts("\n");
  437. for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
  438. m = 0;
  439. printf("%3d (0x%02x) ", k, k);
  440. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  441. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  442. p_8 = (u8 *) &spd[i][j];
  443. if (p_8[k]) {
  444. printf("0x%02x ", p_8[k]);
  445. m++;
  446. } else
  447. puts(" ");
  448. }
  449. }
  450. if (m)
  451. puts("\n");
  452. else
  453. puts("\r");
  454. }
  455. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  456. switch (i) {
  457. case 0:
  458. ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  459. break;
  460. #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  461. case 1:
  462. ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  463. break;
  464. #endif
  465. #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  466. case 2:
  467. ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  468. break;
  469. #endif
  470. #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  471. case 3:
  472. ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  473. break;
  474. #endif
  475. default:
  476. printf("%s unexpected controller number = %u\n",
  477. __func__, i);
  478. return;
  479. }
  480. }
  481. printf("DDR registers dump for all controllers "
  482. "(zero value is omitted)...\n");
  483. puts("Offset (hex) ");
  484. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
  485. printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
  486. puts("\n");
  487. for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
  488. m = 0;
  489. printf("%6d (0x%04x)", k * 4, k * 4);
  490. for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
  491. p_32 = (u32 *) ddr[i];
  492. if (p_32[k]) {
  493. printf(" 0x%08x", p_32[k]);
  494. m++;
  495. } else
  496. puts(" ");
  497. }
  498. if (m)
  499. puts("\n");
  500. else
  501. puts("\r");
  502. }
  503. puts("\n");
  504. }
  505. /* invalid the TLBs for DDR and setup new ones to cover p_addr */
  506. static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
  507. {
  508. u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  509. unsigned long epn;
  510. u32 tsize, valid, ptr;
  511. int ddr_esel;
  512. clear_ddr_tlbs_phys(p_addr, size>>20);
  513. /* Setup new tlb to cover the physical address */
  514. setup_ddr_tlbs_phys(p_addr, size>>20);
  515. ptr = vstart;
  516. ddr_esel = find_tlb_idx((void *)ptr, 1);
  517. if (ddr_esel != -1) {
  518. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
  519. } else {
  520. printf("TLB error in function %s\n", __func__);
  521. return -1;
  522. }
  523. return 0;
  524. }
  525. /*
  526. * slide the testing window up to test another area
  527. * for 32_bit system, the maximum testable memory is limited to
  528. * CONFIG_MAX_MEM_MAPPED
  529. */
  530. int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  531. {
  532. phys_addr_t test_cap, p_addr;
  533. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  534. #if !defined(CONFIG_PHYS_64BIT) || \
  535. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  536. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  537. test_cap = p_size;
  538. #else
  539. test_cap = gd->ram_size;
  540. #endif
  541. p_addr = (*vstart) + (*size) + (*phys_offset);
  542. if (p_addr < test_cap - 1) {
  543. p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
  544. if (reset_tlb(p_addr, p_size, phys_offset) == -1)
  545. return -1;
  546. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  547. *size = (u32) p_size;
  548. printf("Testing 0x%08llx - 0x%08llx\n",
  549. (u64)(*vstart) + (*phys_offset),
  550. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  551. } else
  552. return 1;
  553. return 0;
  554. }
  555. /* initialization for testing area */
  556. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  557. {
  558. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  559. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  560. *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
  561. *phys_offset = 0;
  562. #if !defined(CONFIG_PHYS_64BIT) || \
  563. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  564. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  565. if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
  566. puts("Cannot test more than ");
  567. print_size(CONFIG_MAX_MEM_MAPPED,
  568. " without proper 36BIT support.\n");
  569. }
  570. #endif
  571. printf("Testing 0x%08llx - 0x%08llx\n",
  572. (u64)(*vstart) + (*phys_offset),
  573. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  574. return 0;
  575. }
  576. /* invalid TLBs for DDR and remap as normal after testing */
  577. int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  578. {
  579. unsigned long epn;
  580. u32 tsize, valid, ptr;
  581. phys_addr_t rpn = 0;
  582. int ddr_esel;
  583. /* disable the TLBs for this testing */
  584. ptr = *vstart;
  585. while (ptr < (*vstart) + (*size)) {
  586. ddr_esel = find_tlb_idx((void *)ptr, 1);
  587. if (ddr_esel != -1) {
  588. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
  589. disable_tlb(ddr_esel);
  590. }
  591. ptr += TSIZE_TO_BYTES(tsize);
  592. }
  593. puts("Remap DDR ");
  594. setup_ddr_tlbs(gd->ram_size>>20);
  595. puts("\n");
  596. return 0;
  597. }
  598. void arch_memory_failure_handle(void)
  599. {
  600. dump_spd_ddr_reg();
  601. }
  602. #endif