commproc.c 4.9 KB

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  1. /*
  2. * Adapted for Motorola MPC8560 chips
  3. * Xianghua Xiao <x.xiao@motorola.com>
  4. *
  5. * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
  6. * copyright notice:
  7. *
  8. * General Purpose functions for the global management of the
  9. * 8220 Communication Processor Module.
  10. * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
  11. * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
  12. * 2.3.99 Updates
  13. * Copyright (c) 2003 Motorola,Inc.
  14. *
  15. * In addition to the individual control of the communication
  16. * channels, there are a few functions that globally affect the
  17. * communication processor.
  18. *
  19. * Buffer descriptors must be allocated from the dual ported memory
  20. * space. The allocator for that is here. When the communication
  21. * process is reset, we reclaim the memory available. There is
  22. * currently no deallocator for this memory.
  23. */
  24. #include <common.h>
  25. #include <asm-offsets.h>
  26. #include <asm/cpm_85xx.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /*
  29. * because we have stack and init data in dual port ram
  30. * we must reduce the size
  31. */
  32. #undef CPM_DATAONLY_SIZE
  33. #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
  34. void
  35. m8560_cpm_reset(void)
  36. {
  37. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  38. volatile ulong count;
  39. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  40. /* Reclaim the DP memory for our use.
  41. */
  42. gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
  43. gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
  44. /*
  45. * Reset CPM
  46. */
  47. cpm->im_cpm_cp.cpcr = CPM_CR_RST;
  48. count = 0;
  49. do { /* Spin until command processed */
  50. __asm__ __volatile__ ("eieio");
  51. } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
  52. }
  53. /* Allocate some memory from the dual ported ram.
  54. * To help protocols with object alignment restrictions, we do that
  55. * if they ask.
  56. */
  57. uint
  58. m8560_cpm_dpalloc(uint size, uint align)
  59. {
  60. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  61. uint retloc;
  62. uint align_mask, off;
  63. uint savebase;
  64. align_mask = align - 1;
  65. savebase = gd->arch.dp_alloc_base;
  66. off = gd->arch.dp_alloc_base & align_mask;
  67. if (off != 0)
  68. gd->arch.dp_alloc_base += (align - off);
  69. if ((off = size & align_mask) != 0)
  70. size += align - off;
  71. if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
  72. gd->arch.dp_alloc_base = savebase;
  73. panic("m8560_cpm_dpalloc: ran out of dual port ram!");
  74. }
  75. retloc = gd->arch.dp_alloc_base;
  76. gd->arch.dp_alloc_base += size;
  77. memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
  78. return(retloc);
  79. }
  80. /* We also own one page of host buffer space for the allocation of
  81. * UART "fifos" and the like.
  82. */
  83. uint
  84. m8560_cpm_hostalloc(uint size, uint align)
  85. {
  86. /* the host might not even have RAM yet - just use dual port RAM */
  87. return (m8560_cpm_dpalloc(size, align));
  88. }
  89. /* Set a baud rate generator. This needs lots of work. There are
  90. * eight BRGs, which can be connected to the CPM channels or output
  91. * as clocks. The BRGs are in two different block of internal
  92. * memory mapped space.
  93. * The baud rate clock is the system clock divided by something.
  94. * It was set up long ago during the initial boot phase and is
  95. * is given to us.
  96. * Baud rate clocks are zero-based in the driver code (as that maps
  97. * to port numbers). Documentation uses 1-based numbering.
  98. */
  99. #define BRG_INT_CLK gd->arch.brg_clk
  100. #define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
  101. /* This function is used by UARTS, or anything else that uses a 16x
  102. * oversampled clock.
  103. */
  104. void
  105. m8560_cpm_setbrg(uint brg, uint rate)
  106. {
  107. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  108. volatile uint *bp;
  109. /* This is good enough to get SMCs running.....
  110. */
  111. if (brg < 4) {
  112. bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
  113. }
  114. else {
  115. bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
  116. brg -= 4;
  117. }
  118. bp += brg;
  119. *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
  120. }
  121. /* This function is used to set high speed synchronous baud rate
  122. * clocks.
  123. */
  124. void
  125. m8560_cpm_fastbrg(uint brg, uint rate, int div16)
  126. {
  127. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  128. volatile uint *bp;
  129. /* This is good enough to get SMCs running.....
  130. */
  131. if (brg < 4) {
  132. bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
  133. }
  134. else {
  135. bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
  136. brg -= 4;
  137. }
  138. bp += brg;
  139. *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
  140. if (div16)
  141. *bp |= CPM_BRG_DIV16;
  142. }
  143. /* This function is used to set baud rate generators using an external
  144. * clock source and 16x oversampling.
  145. */
  146. void
  147. m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
  148. {
  149. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  150. volatile uint *bp;
  151. if (brg < 4) {
  152. bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
  153. }
  154. else {
  155. bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
  156. brg -= 4;
  157. }
  158. bp += brg;
  159. *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
  160. if (pinsel == 0)
  161. *bp |= CPM_BRG_EXTC_CLK3_9;
  162. else
  163. *bp |= CPM_BRG_EXTC_CLK5_15;
  164. }