bsc9132_serdes.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
  5. */
  6. #include <config.h>
  7. #include <common.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <asm/immap_85xx.h>
  11. #include <asm/fsl_serdes.h>
  12. #define SRDS1_MAX_LANES 4
  13. static u32 serdes1_prtcl_map;
  14. static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  15. [0] = {NONE, NONE, NONE, NONE},
  16. [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
  17. [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
  18. [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
  19. [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
  20. [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
  21. [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  22. [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  23. [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  24. [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  25. [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  26. [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
  27. [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  28. [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  29. [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  30. [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  31. [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  32. [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  33. [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  34. [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  35. [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  36. [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  37. [22] = {PCIE1, PCIE2, CPRI2, CPRI1},
  38. [23] = {PCIE1, PCIE2, CPRI2, CPRI1},
  39. [24] = {PCIE1, PCIE2, CPRI2, CPRI1},
  40. [25] = {PCIE1, PCIE2, CPRI2, CPRI1},
  41. [26] = {PCIE1, PCIE2, CPRI2, CPRI1},
  42. [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  43. [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  44. [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  45. [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  46. [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
  47. [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
  48. [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  49. [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  50. [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  51. [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  52. [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
  53. [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  54. [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  55. [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  56. [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  57. [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
  58. [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  59. [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  60. [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  61. [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  62. [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
  63. };
  64. int is_serdes_configured(enum srds_prtcl prtcl)
  65. {
  66. if (!(serdes1_prtcl_map & (1 << NONE)))
  67. fsl_serdes_init();
  68. return (1 << prtcl) & serdes1_prtcl_map;
  69. }
  70. void fsl_serdes_init(void)
  71. {
  72. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  73. u32 pordevsr = in_be32(&gur->pordevsr);
  74. u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  75. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  76. int lane;
  77. if (serdes1_prtcl_map & (1 << NONE))
  78. return;
  79. debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
  80. if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  81. printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  82. return;
  83. }
  84. for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  85. enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
  86. serdes1_prtcl_map |= (1 << lane_prtcl);
  87. }
  88. /* Set the first bit to indicate serdes has been initialized */
  89. serdes1_prtcl_map |= (1 << NONE);
  90. }