b4860_serdes.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/fsl_serdes.h>
  7. #include <asm/processor.h>
  8. #include <asm/io.h>
  9. #include "fsl_corenet2_serdes.h"
  10. struct serdes_config {
  11. u8 protocol;
  12. u8 lanes[SRDS_MAX_LANES];
  13. };
  14. #ifdef CONFIG_ARCH_B4860
  15. static struct serdes_config serdes1_cfg_tbl[] = {
  16. /* SerDes 1 */
  17. {0x01, {AURORA, AURORA, CPRI6, CPRI5,
  18. CPRI4, CPRI3, CPRI2, CPRI1} },
  19. {0x02, {AURORA, AURORA, CPRI6, CPRI5,
  20. CPRI4, CPRI3, CPRI2, CPRI1} },
  21. {0x04, {AURORA, AURORA, CPRI6, CPRI5,
  22. CPRI4, CPRI3, CPRI2, CPRI1} },
  23. {0x05, {AURORA, AURORA, CPRI6, CPRI5,
  24. CPRI4, CPRI3, CPRI2, CPRI1} },
  25. {0x06, {AURORA, AURORA, CPRI6, CPRI5,
  26. CPRI4, CPRI3, CPRI2, CPRI1} },
  27. {0x07, {AURORA, AURORA, CPRI6, CPRI5,
  28. CPRI4, CPRI3, CPRI2, CPRI1} },
  29. {0x08, {AURORA, AURORA, CPRI6, CPRI5,
  30. CPRI4, CPRI3, CPRI2, CPRI1} },
  31. {0x09, {AURORA, AURORA, CPRI6, CPRI5,
  32. CPRI4, CPRI3, CPRI2, CPRI1} },
  33. {0x0A, {AURORA, AURORA, CPRI6, CPRI5,
  34. CPRI4, CPRI3, CPRI2, CPRI1} },
  35. {0x0B, {AURORA, AURORA, CPRI6, CPRI5,
  36. CPRI4, CPRI3, CPRI2, CPRI1} },
  37. {0x0C, {AURORA, AURORA, CPRI6, CPRI5,
  38. CPRI4, CPRI3, CPRI2, CPRI1} },
  39. {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
  40. CPRI4, CPRI3, CPRI2, CPRI1}},
  41. {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
  42. CPRI4, CPRI3, CPRI2, CPRI1}},
  43. {0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
  44. CPRI4, CPRI3, CPRI2, CPRI1}},
  45. {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  46. CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
  47. {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  48. CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
  49. {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  50. CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
  51. {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  52. CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
  53. {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  54. CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
  55. {0x2F, {AURORA, AURORA,
  56. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  57. CPRI4, CPRI3, CPRI2, CPRI1} },
  58. {0x30, {AURORA, AURORA,
  59. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  60. CPRI4, CPRI3, CPRI2, CPRI1}},
  61. {0x32, {AURORA, AURORA,
  62. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  63. CPRI4, CPRI3, CPRI2, CPRI1}},
  64. {0x33, {AURORA, AURORA,
  65. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  66. CPRI4, CPRI3, CPRI2, CPRI1}},
  67. {0x34, {AURORA, AURORA,
  68. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  69. CPRI4, CPRI3, CPRI2, CPRI1}},
  70. {0x39, {AURORA, AURORA, CPRI6, CPRI5,
  71. CPRI4, CPRI3, CPRI2, CPRI1} },
  72. {0x3A, {AURORA, AURORA, CPRI6, CPRI5,
  73. CPRI4, CPRI3, CPRI2, CPRI1} },
  74. {0x3C, {AURORA, AURORA, CPRI6, CPRI5,
  75. CPRI4, CPRI3, CPRI2, CPRI1} },
  76. {0x3D, {AURORA, AURORA, CPRI6, CPRI5,
  77. CPRI4, CPRI3, CPRI2, CPRI1} },
  78. {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
  79. CPRI4, CPRI3, CPRI2, CPRI1}},
  80. {0x5C, {AURORA, AURORA,
  81. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  82. CPRI4, CPRI3, CPRI2, CPRI1} },
  83. {0x5D, {AURORA, AURORA,
  84. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  85. CPRI4, CPRI3, CPRI2, CPRI1} },
  86. {}
  87. };
  88. static struct serdes_config serdes2_cfg_tbl[] = {
  89. /* SerDes 2 */
  90. {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  91. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  92. AURORA, AURORA, SRIO1, SRIO1} },
  93. {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  94. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  95. AURORA, AURORA, SRIO1, SRIO1}},
  96. {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  97. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  98. AURORA, AURORA, SRIO1, SRIO1}},
  99. {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  100. SRIO2, SRIO2,
  101. AURORA, AURORA, SRIO1, SRIO1} },
  102. {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  103. SRIO2, SRIO2,
  104. AURORA, AURORA, SRIO1, SRIO1}},
  105. {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  106. SRIO2, SRIO2,
  107. AURORA, AURORA,
  108. SRIO1, SRIO1}},
  109. {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  110. SGMII_FM1_DTSEC3, AURORA,
  111. SRIO1, SRIO1, SRIO1, SRIO1} },
  112. {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  113. SGMII_FM1_DTSEC3, AURORA,
  114. SRIO1, SRIO1, SRIO1, SRIO1}},
  115. {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  116. SGMII_FM1_DTSEC3, AURORA,
  117. SRIO1, SRIO1, SRIO1, SRIO1}},
  118. {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  119. SGMII_FM1_DTSEC3, AURORA,
  120. SRIO1, SRIO1, SRIO1, SRIO1}},
  121. {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  122. SGMII_FM1_DTSEC3, AURORA,
  123. SRIO1, SRIO1, SRIO1, SRIO1}},
  124. {0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
  125. SRIO1, SRIO1, SRIO1, SRIO1} },
  126. {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
  127. SRIO1, SRIO1, SRIO1, SRIO1}},
  128. {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  129. SRIO2, SRIO2, AURORA, AURORA,
  130. XFI_FM1_MAC9, XFI_FM1_MAC10} },
  131. {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  132. SRIO2, SRIO2, AURORA, AURORA,
  133. XFI_FM1_MAC9, XFI_FM1_MAC10}},
  134. {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  135. SRIO2, SRIO2, AURORA, AURORA,
  136. XFI_FM1_MAC9, XFI_FM1_MAC10}},
  137. {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  138. SRIO2, SRIO2,
  139. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  140. XFI_FM1_MAC9, XFI_FM1_MAC10} },
  141. {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  142. SRIO2, SRIO2,
  143. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  144. XFI_FM1_MAC9, XFI_FM1_MAC10}},
  145. {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
  146. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  147. XFI_FM1_MAC9, XFI_FM1_MAC10} },
  148. {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
  149. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  150. XFI_FM1_MAC9, XFI_FM1_MAC10}},
  151. {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  152. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  153. XAUI_FM1_MAC10, XAUI_FM1_MAC10,
  154. XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
  155. {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
  156. XAUI_FM1_MAC10, XAUI_FM1_MAC10,
  157. XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
  158. {0x9A, {PCIE1, PCIE1,
  159. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  160. XAUI_FM1_MAC10, XAUI_FM1_MAC10,
  161. XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
  162. {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
  163. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  164. XFI_FM1_MAC9, XFI_FM1_MAC10} },
  165. {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
  166. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  167. XFI_FM1_MAC9, XFI_FM1_MAC10}},
  168. {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
  169. XAUI_FM1_MAC9, XAUI_FM1_MAC9,
  170. SRIO1, SRIO1, SRIO1, SRIO1}},
  171. {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
  172. XAUI_FM1_MAC9, XAUI_FM1_MAC9,
  173. XAUI_FM1_MAC10, XAUI_FM1_MAC10,
  174. XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
  175. {}
  176. };
  177. #endif
  178. #ifdef CONFIG_ARCH_B4420
  179. static struct serdes_config serdes1_cfg_tbl[] = {
  180. {0x0D, {NONE, NONE, CPRI6, CPRI5,
  181. CPRI4, CPRI3, NONE, NONE} },
  182. {0x0E, {NONE, NONE, CPRI8, CPRI5,
  183. CPRI4, CPRI3, NONE, NONE} },
  184. {0x0F, {NONE, NONE, CPRI6, CPRI5,
  185. CPRI4, CPRI3, NONE, NONE} },
  186. {0x17, {NONE, NONE,
  187. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  188. NONE, NONE, NONE, NONE} },
  189. {0x18, {NONE, NONE,
  190. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  191. NONE, NONE, NONE, NONE} },
  192. {0x1B, {NONE, NONE,
  193. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  194. NONE, NONE, NONE, NONE} },
  195. {0x1D, {NONE, NONE, AURORA, AURORA,
  196. NONE, NONE, NONE, NONE} },
  197. {0x1E, {NONE, NONE, AURORA, AURORA,
  198. NONE, NONE, NONE, NONE} },
  199. {0x21, {NONE, NONE, AURORA, AURORA,
  200. NONE, NONE, NONE, NONE} },
  201. {0x3E, {NONE, NONE, CPRI6, CPRI5,
  202. CPRI4, CPRI3, NONE, NONE} },
  203. {}
  204. };
  205. static struct serdes_config serdes2_cfg_tbl[] = {
  206. {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  207. SGMII_FM1_DTSEC3, AURORA,
  208. NONE, NONE, NONE, NONE} },
  209. {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  210. SGMII_FM1_DTSEC3, AURORA,
  211. NONE, NONE, NONE, NONE} },
  212. {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  213. SGMII_FM1_DTSEC3, AURORA,
  214. NONE, NONE, NONE, NONE} },
  215. {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  216. AURORA, AURORA, NONE, NONE, NONE, NONE} },
  217. {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  218. AURORA, AURORA, NONE, NONE, NONE, NONE} },
  219. {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  220. AURORA, AURORA, NONE, NONE, NONE, NONE} },
  221. {0x99, {PCIE1, PCIE1,
  222. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  223. NONE, NONE, NONE, NONE} },
  224. {0x9A, {PCIE1, PCIE1,
  225. SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  226. NONE, NONE, NONE, NONE} },
  227. {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
  228. NONE, NONE, NONE, NONE} },
  229. {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
  230. NONE, NONE, NONE, NONE} },
  231. {}
  232. };
  233. #endif
  234. static struct serdes_config *serdes_cfg_tbl[] = {
  235. serdes1_cfg_tbl,
  236. serdes2_cfg_tbl,
  237. };
  238. enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
  239. {
  240. struct serdes_config *ptr;
  241. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  242. return 0;
  243. ptr = serdes_cfg_tbl[serdes];
  244. while (ptr->protocol) {
  245. if (ptr->protocol == cfg)
  246. return ptr->lanes[lane];
  247. ptr++;
  248. }
  249. return 0;
  250. }
  251. int is_serdes_prtcl_valid(int serdes, u32 prtcl)
  252. {
  253. int i;
  254. struct serdes_config *ptr;
  255. if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
  256. return 0;
  257. ptr = serdes_cfg_tbl[serdes];
  258. while (ptr->protocol) {
  259. if (ptr->protocol == prtcl)
  260. break;
  261. ptr++;
  262. }
  263. if (!ptr->protocol)
  264. return 0;
  265. for (i = 0; i < SRDS_MAX_LANES; i++) {
  266. if (ptr->lanes[i] != NONE)
  267. return 1;
  268. }
  269. return 0;
  270. }