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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  4. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  5. * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
  6. * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
  7. */
  8. /*
  9. * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
  10. */
  11. #include <asm-offsets.h>
  12. #include <config.h>
  13. #include <mpc83xx.h>
  14. #include <version.h>
  15. #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
  16. #include <ppc_asm.tmpl>
  17. #include <ppc_defs.h>
  18. #include <asm/cache.h>
  19. #include <asm/mmu.h>
  20. #include <asm/u-boot.h>
  21. #include "hrcw/hrcw.h"
  22. #include "bats/bats.h"
  23. #include "hid/hid.h"
  24. /* We don't want the MMU yet.
  25. */
  26. #undef MSR_KERNEL
  27. /*
  28. * Floating Point enable, Machine Check and Recoverable Interr.
  29. */
  30. #ifdef DEBUG
  31. #define MSR_KERNEL (MSR_FP|MSR_RI)
  32. #else
  33. #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
  34. #endif
  35. #if defined(CONFIG_NAND_SPL) || \
  36. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
  37. #define MINIMAL_SPL
  38. #endif
  39. #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
  40. !defined(CONFIG_SYS_RAMBOOT)
  41. #define CONFIG_SYS_FLASHBOOT
  42. #endif
  43. /*
  44. * Set up GOT: Global Offset Table
  45. *
  46. * Use r12 to access the GOT
  47. */
  48. START_GOT
  49. GOT_ENTRY(_GOT2_TABLE_)
  50. GOT_ENTRY(__bss_start)
  51. GOT_ENTRY(__bss_end)
  52. #ifndef MINIMAL_SPL
  53. GOT_ENTRY(_FIXUP_TABLE_)
  54. GOT_ENTRY(_start)
  55. GOT_ENTRY(_start_of_vectors)
  56. GOT_ENTRY(_end_of_vectors)
  57. GOT_ENTRY(transfer_to_handler)
  58. #endif
  59. END_GOT
  60. /*
  61. * The Hard Reset Configuration Word (HRCW) table is in the first 64
  62. * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
  63. * times so the processor can fetch it out of flash whether the flash
  64. * is 8, 16, 32, or 64 bits wide (hardware trickery).
  65. */
  66. .text
  67. #define _HRCW_TABLE_ENTRY(w) \
  68. .fill 8,1,(((w)>>24)&0xff); \
  69. .fill 8,1,(((w)>>16)&0xff); \
  70. .fill 8,1,(((w)>> 8)&0xff); \
  71. .fill 8,1,(((w) )&0xff)
  72. _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
  73. _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
  74. /*
  75. * Magic number and version string - put it after the HRCW since it
  76. * cannot be first in flash like it is in many other processors.
  77. */
  78. .long 0x27051956 /* U-Boot Magic Number */
  79. .globl version_string
  80. version_string:
  81. .ascii U_BOOT_VERSION_STRING, "\0"
  82. .align 2
  83. .globl enable_addr_trans
  84. enable_addr_trans:
  85. /* enable address translation */
  86. mfmsr r5
  87. ori r5, r5, (MSR_IR | MSR_DR)
  88. mtmsr r5
  89. isync
  90. blr
  91. .globl disable_addr_trans
  92. disable_addr_trans:
  93. /* disable address translation */
  94. mflr r4
  95. mfmsr r3
  96. andi. r0, r3, (MSR_IR | MSR_DR)
  97. beqlr
  98. andc r3, r3, r0
  99. mtspr SRR0, r4
  100. mtspr SRR1, r3
  101. rfi
  102. #ifndef CONFIG_DEFAULT_IMMR
  103. #error CONFIG_DEFAULT_IMMR must be defined
  104. #endif /* CONFIG_DEFAULT_IMMR */
  105. #ifndef CONFIG_SYS_IMMR
  106. #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
  107. #endif /* CONFIG_SYS_IMMR */
  108. /*
  109. * After configuration, a system reset exception is executed using the
  110. * vector at offset 0x100 relative to the base set by MSR[IP]. If
  111. * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
  112. * base address is 0xfff00000. In the case of a Power On Reset or Hard
  113. * Reset, the value of MSR[IP] is determined by the CIP field in the
  114. * HRCW.
  115. *
  116. * Other bits in the HRCW set up the Base Address and Port Size in BR0.
  117. * This determines the location of the boot ROM (flash or EPROM) in the
  118. * processor's address space at boot time. As long as the HRCW is set up
  119. * so that we eventually end up executing the code below when the
  120. * processor executes the reset exception, the actual values used should
  121. * not matter.
  122. *
  123. * Once we have got here, the address mask in OR0 is cleared so that the
  124. * bottom 32K of the boot ROM is effectively repeated all throughout the
  125. * processor's address space, after which we can jump to the absolute
  126. * address at which the boot ROM was linked at compile time, and proceed
  127. * to initialise the memory controller without worrying if the rug will
  128. * be pulled out from under us, so to speak (it will be fine as long as
  129. * we configure BR0 with the same boot ROM link address).
  130. */
  131. . = EXC_OFF_SYS_RESET
  132. .globl _start
  133. _start: /* time t 0 */
  134. lis r4, CONFIG_DEFAULT_IMMR@h
  135. nop
  136. mfmsr r5 /* save msr contents */
  137. /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
  138. bl 1f
  139. 1: mflr r7
  140. lis r3, CONFIG_SYS_IMMR@h
  141. ori r3, r3, CONFIG_SYS_IMMR@l
  142. lwz r6, IMMRBAR(r4)
  143. isync
  144. stw r3, IMMRBAR(r4)
  145. lwz r6, 0(r7) /* Arbitrary external load */
  146. isync
  147. lwz r6, IMMRBAR(r3)
  148. isync
  149. /* Initialise the E300 processor core */
  150. /*------------------------------------------*/
  151. #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
  152. defined(CONFIG_NAND_SPL)
  153. /* The FCM begins execution after only the first page
  154. * is loaded. Wait for the rest before branching
  155. * to another flash page.
  156. */
  157. 1: lwz r6, 0x50b0(r3)
  158. andi. r6, r6, 1
  159. beq 1b
  160. #endif
  161. bl init_e300_core
  162. #ifdef CONFIG_SYS_FLASHBOOT
  163. /* Inflate flash location so it appears everywhere, calculate */
  164. /* the absolute address in final location of the FLASH, jump */
  165. /* there and deflate the flash size back to minimal size */
  166. /*------------------------------------------------------------*/
  167. bl map_flash_by_law1
  168. lis r4, (CONFIG_SYS_MONITOR_BASE)@h
  169. ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
  170. addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
  171. mtlr r5
  172. blr
  173. in_flash:
  174. #if 1 /* Remapping flash with LAW0. */
  175. bl remap_flash_by_law0
  176. #endif
  177. #endif /* CONFIG_SYS_FLASHBOOT */
  178. /* setup the bats */
  179. bl setup_bats
  180. sync
  181. /*
  182. * Cache must be enabled here for stack-in-cache trick.
  183. * This means we need to enable the BATS.
  184. * This means:
  185. * 1) for the EVB, original gt regs need to be mapped
  186. * 2) need to have an IBAT for the 0xf region,
  187. * we are running there!
  188. * Cache should be turned on after BATs, since by default
  189. * everything is write-through.
  190. * The init-mem BAT can be reused after reloc. The old
  191. * gt-regs BAT can be reused after board_init_f calls
  192. * board_early_init_f (EVB only).
  193. */
  194. /* enable address translation */
  195. bl enable_addr_trans
  196. sync
  197. /* enable the data cache */
  198. bl dcache_enable
  199. sync
  200. #ifdef CONFIG_SYS_INIT_RAM_LOCK
  201. bl lock_ram_in_cache
  202. sync
  203. #endif
  204. /* set up the stack pointer in our newly created
  205. * cache-ram; use r3 to keep the new SP for now to
  206. * avoid overiding the SP it uselessly */
  207. lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
  208. ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
  209. /* r4 = end of GD area */
  210. addi r4, r3, GENERATED_GBL_DATA_SIZE
  211. /* Zero GD area */
  212. li r0, 0
  213. 1:
  214. subi r4, r4, 1
  215. stb r0, 0(r4)
  216. cmplw r3, r4
  217. bne 1b
  218. #if CONFIG_VAL(SYS_MALLOC_F_LEN)
  219. #if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
  220. #error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
  221. #endif
  222. /* r3 = new stack pointer / pre-reloc malloc area */
  223. subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN)
  224. /* Set pointer to pre-reloc malloc area in GD */
  225. stw r3, GD_MALLOC_BASE(r4)
  226. #endif
  227. li r0, 0 /* Make room for stack frame header and */
  228. stwu r0, -4(r3) /* clear final stack frame so that */
  229. stwu r0, -4(r3) /* stack backtraces terminate cleanly */
  230. /* Finally, actually set SP */
  231. mr r1, r3
  232. /* let the C-code set up the rest */
  233. /* */
  234. /* Be careful to keep code relocatable & stack humble */
  235. /*------------------------------------------------------*/
  236. GET_GOT /* initialize GOT access */
  237. /* Needed for -msingle-pic-base */
  238. bl _GLOBAL_OFFSET_TABLE_@local-4
  239. mflr r30
  240. /* r3: IMMR */
  241. lis r3, CONFIG_SYS_IMMR@h
  242. /* run low-level CPU init code (in Flash)*/
  243. bl cpu_init_f
  244. /* run 1st part of board init code (in Flash)*/
  245. li r3, 0 /* clear boot_flag for calling board_init_f */
  246. bl board_init_f
  247. /* NOTREACHED - board_init_f() does not return */
  248. #ifndef MINIMAL_SPL
  249. /*
  250. * Vector Table
  251. */
  252. .globl _start_of_vectors
  253. _start_of_vectors:
  254. /* Machine check */
  255. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  256. /* Data Storage exception. */
  257. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  258. /* Instruction Storage exception. */
  259. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  260. /* External Interrupt exception. */
  261. #ifndef FIXME
  262. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  263. #endif
  264. /* Alignment exception. */
  265. . = 0x600
  266. Alignment:
  267. EXCEPTION_PROLOG(SRR0, SRR1)
  268. mfspr r4,DAR
  269. stw r4,_DAR(r21)
  270. mfspr r5,DSISR
  271. stw r5,_DSISR(r21)
  272. addi r3,r1,STACK_FRAME_OVERHEAD
  273. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  274. /* Program check exception */
  275. . = 0x700
  276. ProgramCheck:
  277. EXCEPTION_PROLOG(SRR0, SRR1)
  278. addi r3,r1,STACK_FRAME_OVERHEAD
  279. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  280. MSR_KERNEL, COPY_EE)
  281. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  282. /* I guess we could implement decrementer, and may have
  283. * to someday for timekeeping.
  284. */
  285. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  286. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  287. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  288. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  289. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  290. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  291. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  292. STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
  293. STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
  294. STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
  295. #ifdef DEBUG
  296. . = 0x1300
  297. /*
  298. * This exception occurs when the program counter matches the
  299. * Instruction Address Breakpoint Register (IABR).
  300. *
  301. * I want the cpu to halt if this occurs so I can hunt around
  302. * with the debugger and look at things.
  303. *
  304. * When DEBUG is defined, both machine check enable (in the MSR)
  305. * and checkstop reset enable (in the reset mode register) are
  306. * turned off and so a checkstop condition will result in the cpu
  307. * halting.
  308. *
  309. * I force the cpu into a checkstop condition by putting an illegal
  310. * instruction here (at least this is the theory).
  311. *
  312. * well - that didnt work, so just do an infinite loop!
  313. */
  314. 1: b 1b
  315. #else
  316. STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
  317. #endif
  318. STD_EXCEPTION(0x1400, SMI, UnknownException)
  319. STD_EXCEPTION(0x1500, Trap_15, UnknownException)
  320. STD_EXCEPTION(0x1600, Trap_16, UnknownException)
  321. STD_EXCEPTION(0x1700, Trap_17, UnknownException)
  322. STD_EXCEPTION(0x1800, Trap_18, UnknownException)
  323. STD_EXCEPTION(0x1900, Trap_19, UnknownException)
  324. STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
  325. STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
  326. STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
  327. STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
  328. STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
  329. STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
  330. STD_EXCEPTION(0x2000, Trap_20, UnknownException)
  331. STD_EXCEPTION(0x2100, Trap_21, UnknownException)
  332. STD_EXCEPTION(0x2200, Trap_22, UnknownException)
  333. STD_EXCEPTION(0x2300, Trap_23, UnknownException)
  334. STD_EXCEPTION(0x2400, Trap_24, UnknownException)
  335. STD_EXCEPTION(0x2500, Trap_25, UnknownException)
  336. STD_EXCEPTION(0x2600, Trap_26, UnknownException)
  337. STD_EXCEPTION(0x2700, Trap_27, UnknownException)
  338. STD_EXCEPTION(0x2800, Trap_28, UnknownException)
  339. STD_EXCEPTION(0x2900, Trap_29, UnknownException)
  340. STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
  341. STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
  342. STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
  343. STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
  344. STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
  345. STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
  346. .globl _end_of_vectors
  347. _end_of_vectors:
  348. . = 0x3000
  349. /*
  350. * This code finishes saving the registers to the exception frame
  351. * and jumps to the appropriate handler for the exception.
  352. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  353. */
  354. .globl transfer_to_handler
  355. transfer_to_handler:
  356. stw r22,_NIP(r21)
  357. lis r22,MSR_POW@h
  358. andc r23,r23,r22
  359. stw r23,_MSR(r21)
  360. SAVE_GPR(7, r21)
  361. SAVE_4GPRS(8, r21)
  362. SAVE_8GPRS(12, r21)
  363. SAVE_8GPRS(24, r21)
  364. mflr r23
  365. andi. r24,r23,0x3f00 /* get vector offset */
  366. stw r24,TRAP(r21)
  367. li r22,0
  368. stw r22,RESULT(r21)
  369. lwz r24,0(r23) /* virtual address of handler */
  370. lwz r23,4(r23) /* where to go when done */
  371. mtspr SRR0,r24
  372. mtspr SRR1,r20
  373. mtlr r23
  374. SYNC
  375. rfi /* jump to handler, enable MMU */
  376. int_return:
  377. mfmsr r28 /* Disable interrupts */
  378. li r4,0
  379. ori r4,r4,MSR_EE
  380. andc r28,r28,r4
  381. SYNC /* Some chip revs need this... */
  382. mtmsr r28
  383. SYNC
  384. lwz r2,_CTR(r1)
  385. lwz r0,_LINK(r1)
  386. mtctr r2
  387. mtlr r0
  388. lwz r2,_XER(r1)
  389. lwz r0,_CCR(r1)
  390. mtspr XER,r2
  391. mtcrf 0xFF,r0
  392. REST_10GPRS(3, r1)
  393. REST_10GPRS(13, r1)
  394. REST_8GPRS(23, r1)
  395. REST_GPR(31, r1)
  396. lwz r2,_NIP(r1) /* Restore environment */
  397. lwz r0,_MSR(r1)
  398. mtspr SRR0,r2
  399. mtspr SRR1,r0
  400. lwz r0,GPR0(r1)
  401. lwz r2,GPR2(r1)
  402. lwz r1,GPR1(r1)
  403. SYNC
  404. rfi
  405. #endif /* !MINIMAL_SPL */
  406. /*
  407. * This code initialises the E300 processor core
  408. * (conforms to PowerPC 603e spec)
  409. * Note: expects original MSR contents to be in r5.
  410. */
  411. .globl init_e300_core
  412. init_e300_core: /* time t 10 */
  413. /* Initialize machine status; enable machine check interrupt */
  414. /*-----------------------------------------------------------*/
  415. li r3, MSR_KERNEL /* Set ME and RI flags */
  416. rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
  417. #ifdef DEBUG
  418. rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
  419. #endif
  420. SYNC /* Some chip revs need this... */
  421. mtmsr r3
  422. SYNC
  423. mtspr SRR1, r3 /* Make SRR1 match MSR */
  424. lis r3, CONFIG_SYS_IMMR@h
  425. #if defined(CONFIG_WATCHDOG)
  426. /* Initialise the Watchdog values and reset it (if req) */
  427. /*------------------------------------------------------*/
  428. lis r4, CONFIG_SYS_WATCHDOG_VALUE
  429. ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
  430. stw r4, SWCRR(r3)
  431. /* and reset it */
  432. li r4, 0x556C
  433. sth r4, SWSRR@l(r3)
  434. li r4, -0x55C7
  435. sth r4, SWSRR@l(r3)
  436. #else
  437. /* Disable Watchdog */
  438. /*-------------------*/
  439. lwz r4, SWCRR(r3)
  440. /* Check to see if its enabled for disabling
  441. once disabled by SW you can't re-enable */
  442. andi. r4, r4, 0x4
  443. beq 1f
  444. xor r4, r4, r4
  445. stw r4, SWCRR(r3)
  446. 1:
  447. #endif /* CONFIG_WATCHDOG */
  448. #if defined(CONFIG_MASK_AER_AO)
  449. /* Write the Arbiter Event Enable to mask Address Only traps. */
  450. /* This prevents the dcbz instruction from being trapped when */
  451. /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
  452. /* COHERENCY bit is set in the WIMG bits, which is often */
  453. /* needed for PCI operation. */
  454. lwz r4, 0x0808(r3)
  455. rlwinm r0, r4, 0, ~AER_AO
  456. stw r0, 0x0808(r3)
  457. #endif /* CONFIG_MASK_AER_AO */
  458. /* Initialize the Hardware Implementation-dependent Registers */
  459. /* HID0 also contains cache control */
  460. /* - force invalidation of data and instruction caches */
  461. /*------------------------------------------------------*/
  462. lis r3, CONFIG_SYS_HID0_INIT@h
  463. ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
  464. SYNC
  465. mtspr HID0, r3
  466. lis r3, CONFIG_SYS_HID0_FINAL@h
  467. ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
  468. SYNC
  469. mtspr HID0, r3
  470. lis r3, CONFIG_SYS_HID2@h
  471. ori r3, r3, CONFIG_SYS_HID2@l
  472. SYNC
  473. mtspr HID2, r3
  474. /* Done! */
  475. /*------------------------------*/
  476. blr
  477. /* setup_bats - set them up to some initial state */
  478. .globl setup_bats
  479. setup_bats:
  480. addis r0, r0, 0x0000
  481. /* IBAT 0 */
  482. addis r4, r0, CONFIG_SYS_IBAT0L@h
  483. ori r4, r4, CONFIG_SYS_IBAT0L@l
  484. addis r3, r0, CONFIG_SYS_IBAT0U@h
  485. ori r3, r3, CONFIG_SYS_IBAT0U@l
  486. mtspr IBAT0L, r4
  487. mtspr IBAT0U, r3
  488. /* DBAT 0 */
  489. addis r4, r0, CONFIG_SYS_DBAT0L@h
  490. ori r4, r4, CONFIG_SYS_DBAT0L@l
  491. addis r3, r0, CONFIG_SYS_DBAT0U@h
  492. ori r3, r3, CONFIG_SYS_DBAT0U@l
  493. mtspr DBAT0L, r4
  494. mtspr DBAT0U, r3
  495. /* IBAT 1 */
  496. addis r4, r0, CONFIG_SYS_IBAT1L@h
  497. ori r4, r4, CONFIG_SYS_IBAT1L@l
  498. addis r3, r0, CONFIG_SYS_IBAT1U@h
  499. ori r3, r3, CONFIG_SYS_IBAT1U@l
  500. mtspr IBAT1L, r4
  501. mtspr IBAT1U, r3
  502. /* DBAT 1 */
  503. addis r4, r0, CONFIG_SYS_DBAT1L@h
  504. ori r4, r4, CONFIG_SYS_DBAT1L@l
  505. addis r3, r0, CONFIG_SYS_DBAT1U@h
  506. ori r3, r3, CONFIG_SYS_DBAT1U@l
  507. mtspr DBAT1L, r4
  508. mtspr DBAT1U, r3
  509. /* IBAT 2 */
  510. addis r4, r0, CONFIG_SYS_IBAT2L@h
  511. ori r4, r4, CONFIG_SYS_IBAT2L@l
  512. addis r3, r0, CONFIG_SYS_IBAT2U@h
  513. ori r3, r3, CONFIG_SYS_IBAT2U@l
  514. mtspr IBAT2L, r4
  515. mtspr IBAT2U, r3
  516. /* DBAT 2 */
  517. addis r4, r0, CONFIG_SYS_DBAT2L@h
  518. ori r4, r4, CONFIG_SYS_DBAT2L@l
  519. addis r3, r0, CONFIG_SYS_DBAT2U@h
  520. ori r3, r3, CONFIG_SYS_DBAT2U@l
  521. mtspr DBAT2L, r4
  522. mtspr DBAT2U, r3
  523. /* IBAT 3 */
  524. addis r4, r0, CONFIG_SYS_IBAT3L@h
  525. ori r4, r4, CONFIG_SYS_IBAT3L@l
  526. addis r3, r0, CONFIG_SYS_IBAT3U@h
  527. ori r3, r3, CONFIG_SYS_IBAT3U@l
  528. mtspr IBAT3L, r4
  529. mtspr IBAT3U, r3
  530. /* DBAT 3 */
  531. addis r4, r0, CONFIG_SYS_DBAT3L@h
  532. ori r4, r4, CONFIG_SYS_DBAT3L@l
  533. addis r3, r0, CONFIG_SYS_DBAT3U@h
  534. ori r3, r3, CONFIG_SYS_DBAT3U@l
  535. mtspr DBAT3L, r4
  536. mtspr DBAT3U, r3
  537. #ifdef CONFIG_HIGH_BATS
  538. /* IBAT 4 */
  539. addis r4, r0, CONFIG_SYS_IBAT4L@h
  540. ori r4, r4, CONFIG_SYS_IBAT4L@l
  541. addis r3, r0, CONFIG_SYS_IBAT4U@h
  542. ori r3, r3, CONFIG_SYS_IBAT4U@l
  543. mtspr IBAT4L, r4
  544. mtspr IBAT4U, r3
  545. /* DBAT 4 */
  546. addis r4, r0, CONFIG_SYS_DBAT4L@h
  547. ori r4, r4, CONFIG_SYS_DBAT4L@l
  548. addis r3, r0, CONFIG_SYS_DBAT4U@h
  549. ori r3, r3, CONFIG_SYS_DBAT4U@l
  550. mtspr DBAT4L, r4
  551. mtspr DBAT4U, r3
  552. /* IBAT 5 */
  553. addis r4, r0, CONFIG_SYS_IBAT5L@h
  554. ori r4, r4, CONFIG_SYS_IBAT5L@l
  555. addis r3, r0, CONFIG_SYS_IBAT5U@h
  556. ori r3, r3, CONFIG_SYS_IBAT5U@l
  557. mtspr IBAT5L, r4
  558. mtspr IBAT5U, r3
  559. /* DBAT 5 */
  560. addis r4, r0, CONFIG_SYS_DBAT5L@h
  561. ori r4, r4, CONFIG_SYS_DBAT5L@l
  562. addis r3, r0, CONFIG_SYS_DBAT5U@h
  563. ori r3, r3, CONFIG_SYS_DBAT5U@l
  564. mtspr DBAT5L, r4
  565. mtspr DBAT5U, r3
  566. /* IBAT 6 */
  567. addis r4, r0, CONFIG_SYS_IBAT6L@h
  568. ori r4, r4, CONFIG_SYS_IBAT6L@l
  569. addis r3, r0, CONFIG_SYS_IBAT6U@h
  570. ori r3, r3, CONFIG_SYS_IBAT6U@l
  571. mtspr IBAT6L, r4
  572. mtspr IBAT6U, r3
  573. /* DBAT 6 */
  574. addis r4, r0, CONFIG_SYS_DBAT6L@h
  575. ori r4, r4, CONFIG_SYS_DBAT6L@l
  576. addis r3, r0, CONFIG_SYS_DBAT6U@h
  577. ori r3, r3, CONFIG_SYS_DBAT6U@l
  578. mtspr DBAT6L, r4
  579. mtspr DBAT6U, r3
  580. /* IBAT 7 */
  581. addis r4, r0, CONFIG_SYS_IBAT7L@h
  582. ori r4, r4, CONFIG_SYS_IBAT7L@l
  583. addis r3, r0, CONFIG_SYS_IBAT7U@h
  584. ori r3, r3, CONFIG_SYS_IBAT7U@l
  585. mtspr IBAT7L, r4
  586. mtspr IBAT7U, r3
  587. /* DBAT 7 */
  588. addis r4, r0, CONFIG_SYS_DBAT7L@h
  589. ori r4, r4, CONFIG_SYS_DBAT7L@l
  590. addis r3, r0, CONFIG_SYS_DBAT7U@h
  591. ori r3, r3, CONFIG_SYS_DBAT7U@l
  592. mtspr DBAT7L, r4
  593. mtspr DBAT7U, r3
  594. #endif
  595. isync
  596. /* invalidate all tlb's
  597. *
  598. * From the 603e User Manual: "The 603e provides the ability to
  599. * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
  600. * instruction invalidates the TLB entry indexed by the EA, and
  601. * operates on both the instruction and data TLBs simultaneously
  602. * invalidating four TLB entries (both sets in each TLB). The
  603. * index corresponds to bits 15-19 of the EA. To invalidate all
  604. * entries within both TLBs, 32 tlbie instructions should be
  605. * issued, incrementing this field by one each time."
  606. *
  607. * "Note that the tlbia instruction is not implemented on the
  608. * 603e."
  609. *
  610. * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
  611. * incrementing by 0x1000 each time. The code below is sort of
  612. * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
  613. *
  614. */
  615. lis r3, 0
  616. lis r5, 2
  617. 1:
  618. tlbie r3
  619. addi r3, r3, 0x1000
  620. cmp 0, 0, r3, r5
  621. blt 1b
  622. blr
  623. /* Cache functions.
  624. *
  625. * Note: requires that all cache bits in
  626. * HID0 are in the low half word.
  627. */
  628. #ifndef MINIMAL_SPL
  629. .globl icache_enable
  630. icache_enable:
  631. mfspr r3, HID0
  632. ori r3, r3, HID0_ICE
  633. li r4, HID0_ICFI|HID0_ILOCK
  634. andc r3, r3, r4
  635. ori r4, r3, HID0_ICFI
  636. isync
  637. mtspr HID0, r4 /* sets enable and invalidate, clears lock */
  638. isync
  639. mtspr HID0, r3 /* clears invalidate */
  640. blr
  641. .globl icache_disable
  642. icache_disable:
  643. mfspr r3, HID0
  644. lis r4, 0
  645. ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
  646. andc r3, r3, r4
  647. isync
  648. mtspr HID0, r3 /* clears invalidate, enable and lock */
  649. blr
  650. .globl icache_status
  651. icache_status:
  652. mfspr r3, HID0
  653. rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
  654. blr
  655. #endif /* !MINIMAL_SPL */
  656. .globl dcache_enable
  657. dcache_enable:
  658. mfspr r3, HID0
  659. li r5, HID0_DCFI|HID0_DLOCK
  660. andc r3, r3, r5
  661. ori r3, r3, HID0_DCE
  662. sync
  663. mtspr HID0, r3 /* enable, no invalidate */
  664. blr
  665. .globl dcache_disable
  666. dcache_disable:
  667. mflr r4
  668. bl flush_dcache /* uses r3 and r5 */
  669. mfspr r3, HID0
  670. li r5, HID0_DCE|HID0_DLOCK
  671. andc r3, r3, r5
  672. ori r5, r3, HID0_DCFI
  673. sync
  674. mtspr HID0, r5 /* sets invalidate, clears enable and lock */
  675. sync
  676. mtspr HID0, r3 /* clears invalidate */
  677. mtlr r4
  678. blr
  679. .globl dcache_status
  680. dcache_status:
  681. mfspr r3, HID0
  682. rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
  683. blr
  684. .globl flush_dcache
  685. flush_dcache:
  686. lis r3, 0
  687. lis r5, CONFIG_SYS_CACHELINE_SIZE
  688. 1: cmp 0, 1, r3, r5
  689. bge 2f
  690. lwz r5, 0(r3)
  691. lis r5, CONFIG_SYS_CACHELINE_SIZE
  692. addi r3, r3, 0x4
  693. b 1b
  694. 2: blr
  695. /*-------------------------------------------------------------------*/
  696. /*
  697. * void relocate_code(addr_sp, gd, addr_moni)
  698. *
  699. * This "function" does not return, instead it continues in RAM
  700. * after relocating the monitor code.
  701. *
  702. * r3 = dest
  703. * r4 = src
  704. * r5 = length in bytes
  705. * r6 = cachelinesize
  706. */
  707. .globl relocate_code
  708. relocate_code:
  709. mr r1, r3 /* Set new stack pointer */
  710. mr r9, r4 /* Save copy of Global Data pointer */
  711. mr r10, r5 /* Save copy of Destination Address */
  712. GET_GOT
  713. mr r3, r5 /* Destination Address */
  714. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  715. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  716. lwz r5, GOT(__bss_start)
  717. sub r5, r5, r4
  718. li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  719. /*
  720. * Fix GOT pointer:
  721. *
  722. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
  723. * + Destination Address
  724. *
  725. * Offset:
  726. */
  727. sub r15, r10, r4
  728. /* First our own GOT */
  729. add r12, r12, r15
  730. /* then the one used by the C code */
  731. add r30, r30, r15
  732. /*
  733. * Now relocate code
  734. */
  735. cmplw cr1,r3,r4
  736. addi r0,r5,3
  737. srwi. r0,r0,2
  738. beq cr1,4f /* In place copy is not necessary */
  739. beq 7f /* Protect against 0 count */
  740. mtctr r0
  741. bge cr1,2f
  742. la r8,-4(r4)
  743. la r7,-4(r3)
  744. /* copy */
  745. 1: lwzu r0,4(r8)
  746. stwu r0,4(r7)
  747. bdnz 1b
  748. addi r0,r5,3
  749. srwi. r0,r0,2
  750. mtctr r0
  751. la r8,-4(r4)
  752. la r7,-4(r3)
  753. /* and compare */
  754. 20: lwzu r20,4(r8)
  755. lwzu r21,4(r7)
  756. xor. r22, r20, r21
  757. bne 30f
  758. bdnz 20b
  759. b 4f
  760. /* compare failed */
  761. 30: li r3, 0
  762. blr
  763. 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
  764. add r8,r4,r0
  765. add r7,r3,r0
  766. 3: lwzu r0,-4(r8)
  767. stwu r0,-4(r7)
  768. bdnz 3b
  769. /*
  770. * Now flush the cache: note that we must start from a cache aligned
  771. * address. Otherwise we might miss one cache line.
  772. */
  773. 4: cmpwi r6,0
  774. add r5,r3,r5
  775. beq 7f /* Always flush prefetch queue in any case */
  776. subi r0,r6,1
  777. andc r3,r3,r0
  778. mr r4,r3
  779. 5: dcbst 0,r4
  780. add r4,r4,r6
  781. cmplw r4,r5
  782. blt 5b
  783. sync /* Wait for all dcbst to complete on bus */
  784. mr r4,r3
  785. 6: icbi 0,r4
  786. add r4,r4,r6
  787. cmplw r4,r5
  788. blt 6b
  789. 7: sync /* Wait for all icbi to complete on bus */
  790. isync
  791. /*
  792. * We are done. Do not return, instead branch to second part of board
  793. * initialization, now running from RAM.
  794. */
  795. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  796. mtlr r0
  797. blr
  798. in_ram:
  799. /*
  800. * Relocation Function, r12 point to got2+0x8000
  801. *
  802. * Adjust got2 pointers, no need to check for 0, this code
  803. * already puts a few entries in the table.
  804. */
  805. li r0,__got2_entries@sectoff@l
  806. la r3,GOT(_GOT2_TABLE_)
  807. lwz r11,GOT(_GOT2_TABLE_)
  808. mtctr r0
  809. sub r11,r3,r11
  810. addi r3,r3,-4
  811. 1: lwzu r0,4(r3)
  812. cmpwi r0,0
  813. beq- 2f
  814. add r0,r0,r11
  815. stw r0,0(r3)
  816. 2: bdnz 1b
  817. #ifndef MINIMAL_SPL
  818. /*
  819. * Now adjust the fixups and the pointers to the fixups
  820. * in case we need to move ourselves again.
  821. */
  822. li r0,__fixup_entries@sectoff@l
  823. lwz r3,GOT(_FIXUP_TABLE_)
  824. cmpwi r0,0
  825. mtctr r0
  826. addi r3,r3,-4
  827. beq 4f
  828. 3: lwzu r4,4(r3)
  829. lwzux r0,r4,r11
  830. cmpwi r0,0
  831. add r0,r0,r11
  832. stw r4,0(r3)
  833. beq- 5f
  834. stw r0,0(r4)
  835. 5: bdnz 3b
  836. 4:
  837. #endif
  838. clear_bss:
  839. /*
  840. * Now clear BSS segment
  841. */
  842. lwz r3,GOT(__bss_start)
  843. lwz r4,GOT(__bss_end)
  844. cmplw 0, r3, r4
  845. beq 6f
  846. li r0, 0
  847. 5:
  848. stw r0, 0(r3)
  849. addi r3, r3, 4
  850. cmplw 0, r3, r4
  851. bne 5b
  852. 6:
  853. mr r3, r9 /* Global Data pointer */
  854. mr r4, r10 /* Destination Address */
  855. bl board_init_r
  856. #ifndef MINIMAL_SPL
  857. /*
  858. * Copy exception vector code to low memory
  859. *
  860. * r3: dest_addr
  861. * r7: source address, r8: end address, r9: target address
  862. */
  863. .globl trap_init
  864. trap_init:
  865. mflr r4 /* save link register */
  866. GET_GOT
  867. lwz r7, GOT(_start)
  868. lwz r8, GOT(_end_of_vectors)
  869. li r9, 0x100 /* reset vector always at 0x100 */
  870. cmplw 0, r7, r8
  871. bgelr /* return if r7>=r8 - just in case */
  872. 1:
  873. lwz r0, 0(r7)
  874. stw r0, 0(r9)
  875. addi r7, r7, 4
  876. addi r9, r9, 4
  877. cmplw 0, r7, r8
  878. bne 1b
  879. /*
  880. * relocate `hdlr' and `int_return' entries
  881. */
  882. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  883. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  884. 2:
  885. bl trap_reloc
  886. addi r7, r7, 0x100 /* next exception vector */
  887. cmplw 0, r7, r8
  888. blt 2b
  889. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  890. bl trap_reloc
  891. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  892. bl trap_reloc
  893. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  894. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  895. 3:
  896. bl trap_reloc
  897. addi r7, r7, 0x100 /* next exception vector */
  898. cmplw 0, r7, r8
  899. blt 3b
  900. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  901. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  902. 4:
  903. bl trap_reloc
  904. addi r7, r7, 0x100 /* next exception vector */
  905. cmplw 0, r7, r8
  906. blt 4b
  907. mfmsr r3 /* now that the vectors have */
  908. lis r7, MSR_IP@h /* relocated into low memory */
  909. ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
  910. andc r3, r3, r7 /* (if it was on) */
  911. SYNC /* Some chip revs need this... */
  912. mtmsr r3
  913. SYNC
  914. mtlr r4 /* restore link register */
  915. blr
  916. #endif /* !MINIMAL_SPL */
  917. #ifdef CONFIG_SYS_INIT_RAM_LOCK
  918. lock_ram_in_cache:
  919. /* Allocate Initial RAM in data cache.
  920. */
  921. lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
  922. ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
  923. li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
  924. (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
  925. mtctr r4
  926. 1:
  927. dcbz r0, r3
  928. addi r3, r3, 32
  929. bdnz 1b
  930. /* Lock the data cache */
  931. mfspr r0, HID0
  932. ori r0, r0, HID0_DLOCK
  933. sync
  934. mtspr HID0, r0
  935. sync
  936. blr
  937. #ifndef MINIMAL_SPL
  938. .globl unlock_ram_in_cache
  939. unlock_ram_in_cache:
  940. /* invalidate the INIT_RAM section */
  941. lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
  942. ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
  943. li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
  944. (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
  945. mtctr r4
  946. 1: icbi r0, r3
  947. dcbi r0, r3
  948. addi r3, r3, 32
  949. bdnz 1b
  950. sync /* Wait for all icbi to complete on bus */
  951. isync
  952. /* Unlock the data cache and invalidate it */
  953. mfspr r3, HID0
  954. li r5, HID0_DLOCK|HID0_DCFI
  955. andc r3, r3, r5 /* no invalidate, unlock */
  956. ori r5, r3, HID0_DCFI /* invalidate, unlock */
  957. sync
  958. mtspr HID0, r5 /* invalidate, unlock */
  959. sync
  960. mtspr HID0, r3 /* no invalidate, unlock */
  961. blr
  962. #endif /* !MINIMAL_SPL */
  963. #endif /* CONFIG_SYS_INIT_RAM_LOCK */
  964. #ifdef CONFIG_SYS_FLASHBOOT
  965. map_flash_by_law1:
  966. /* When booting from ROM (Flash or EPROM), clear the */
  967. /* Address Mask in OR0 so ROM appears everywhere */
  968. /*----------------------------------------------------*/
  969. lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
  970. lwz r4, OR0@l(r3)
  971. li r5, 0x7fff /* r5 <= 0x00007FFFF */
  972. and r4, r4, r5
  973. stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
  974. /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
  975. * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
  976. * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
  977. * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
  978. * 0xFF800. From the hard resetting to here, the processor fetched and
  979. * executed the instructions one by one. There is not absolutely
  980. * jumping happened. Laterly, the u-boot code has to do an absolutely
  981. * jumping to tell the CPU instruction fetching component what the
  982. * u-boot TEXT base address is. Because the TEXT base resides in the
  983. * boot ROM memory space, to garantee the code can run smoothly after
  984. * that jumping, we must map in the entire boot ROM by Local Access
  985. * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
  986. * address for boot ROM, such as 0xFE000000. In this case, the default
  987. * LBIU Local Access Widow 0 will not cover this memory space. So, we
  988. * need another window to map in it.
  989. */
  990. lis r4, (CONFIG_SYS_FLASH_BASE)@h
  991. ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
  992. stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
  993. /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
  994. lis r4, (0x80000012)@h
  995. ori r4, r4, (0x80000012)@l
  996. li r5, CONFIG_SYS_FLASH_SIZE
  997. 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
  998. addi r4, r4, 1
  999. bne 1b
  1000. stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
  1001. /* Wait for HW to catch up */
  1002. lwz r4, LBLAWAR1(r3)
  1003. twi 0,r4,0
  1004. isync
  1005. blr
  1006. /* Though all the LBIU Local Access Windows and LBC Banks will be
  1007. * initialized in the C code, we'd better configure boot ROM's
  1008. * window 0 and bank 0 correctly at here.
  1009. */
  1010. remap_flash_by_law0:
  1011. /* Initialize the BR0 with the boot ROM starting address. */
  1012. lwz r4, BR0(r3)
  1013. li r5, 0x7FFF
  1014. and r4, r4, r5
  1015. lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
  1016. ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
  1017. or r5, r5, r4
  1018. stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
  1019. lwz r4, OR0(r3)
  1020. lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
  1021. or r4, r4, r5
  1022. stw r4, OR0(r3)
  1023. lis r4, (CONFIG_SYS_FLASH_BASE)@h
  1024. ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
  1025. stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
  1026. /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
  1027. lis r4, (0x80000012)@h
  1028. ori r4, r4, (0x80000012)@l
  1029. li r5, CONFIG_SYS_FLASH_SIZE
  1030. 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
  1031. addi r4, r4, 1
  1032. bne 1b
  1033. stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
  1034. xor r4, r4, r4
  1035. stw r4, LBLAWBAR1(r3)
  1036. stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
  1037. /* Wait for HW to catch up */
  1038. lwz r4, LBLAWAR1(r3)
  1039. twi 0,r4,0
  1040. isync
  1041. blr
  1042. #endif /* CONFIG_SYS_FLASHBOOT */