spd_sdram.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2006
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  9. * (C) Copyright 2003 Motorola Inc.
  10. * Xianghua Xiao (X.Xiao@motorola.com)
  11. */
  12. #ifndef CONFIG_MPC83XX_SDRAM
  13. #include <common.h>
  14. #include <cpu_func.h>
  15. #include <log.h>
  16. #include <time.h>
  17. #include <vsprintf.h>
  18. #include <asm/processor.h>
  19. #include <asm/io.h>
  20. #include <i2c.h>
  21. #include <spd.h>
  22. #include <asm/mmu.h>
  23. #include <spd_sdram.h>
  24. #include <asm/bitops.h>
  25. #include <linux/delay.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. void board_add_ram_info(int use_default)
  28. {
  29. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  30. volatile ddr83xx_t *ddr = &immap->ddr;
  31. char buf[32];
  32. printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
  33. >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
  34. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
  35. if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
  36. puts(", 16-bit");
  37. else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
  38. puts(", 32-bit");
  39. else
  40. puts(", unknown width");
  41. #else
  42. if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
  43. puts(", 32-bit");
  44. else
  45. puts(", 64-bit");
  46. #endif
  47. if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
  48. puts(", ECC on");
  49. else
  50. puts(", ECC off");
  51. printf(", %s MHz)", strmhz(buf, gd->mem_clk));
  52. #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
  53. puts("\nSDRAM: ");
  54. print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
  55. #endif
  56. }
  57. #ifdef CONFIG_SPD_EEPROM
  58. #ifndef CONFIG_SYS_READ_SPD
  59. #define CONFIG_SYS_READ_SPD i2c_read
  60. #endif
  61. #ifndef SPD_EEPROM_OFFSET
  62. #define SPD_EEPROM_OFFSET 0
  63. #endif
  64. #ifndef SPD_EEPROM_ADDR_LEN
  65. #define SPD_EEPROM_ADDR_LEN 1
  66. #endif
  67. /*
  68. * Convert picoseconds into clock cycles (rounding up if needed).
  69. */
  70. int
  71. picos_to_clk(int picos)
  72. {
  73. unsigned int mem_bus_clk;
  74. int clks;
  75. mem_bus_clk = gd->mem_clk >> 1;
  76. clks = picos / (1000000000 / (mem_bus_clk / 1000));
  77. if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
  78. clks++;
  79. return clks;
  80. }
  81. unsigned int banksize(unsigned char row_dens)
  82. {
  83. return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
  84. }
  85. int read_spd(uint addr)
  86. {
  87. return ((int) addr);
  88. }
  89. #undef SPD_DEBUG
  90. #ifdef SPD_DEBUG
  91. static void spd_debug(spd_eeprom_t *spd)
  92. {
  93. printf ("\nDIMM type: %-18.18s\n", spd->mpart);
  94. printf ("SPD size: %d\n", spd->info_size);
  95. printf ("EEPROM size: %d\n", 1 << spd->chip_size);
  96. printf ("Memory type: %d\n", spd->mem_type);
  97. printf ("Row addr: %d\n", spd->nrow_addr);
  98. printf ("Column addr: %d\n", spd->ncol_addr);
  99. printf ("# of rows: %d\n", spd->nrows);
  100. printf ("Row density: %d\n", spd->row_dens);
  101. printf ("# of banks: %d\n", spd->nbanks);
  102. printf ("Data width: %d\n",
  103. 256 * spd->dataw_msb + spd->dataw_lsb);
  104. printf ("Chip width: %d\n", spd->primw);
  105. printf ("Refresh rate: %02X\n", spd->refresh);
  106. printf ("CAS latencies: %02X\n", spd->cas_lat);
  107. printf ("Write latencies: %02X\n", spd->write_lat);
  108. printf ("tRP: %d\n", spd->trp);
  109. printf ("tRCD: %d\n", spd->trcd);
  110. printf ("\n");
  111. }
  112. #endif /* SPD_DEBUG */
  113. long int spd_sdram()
  114. {
  115. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  116. volatile ddr83xx_t *ddr = &immap->ddr;
  117. volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
  118. spd_eeprom_t spd;
  119. unsigned int n_ranks;
  120. unsigned int odt_rd_cfg, odt_wr_cfg;
  121. unsigned char twr_clk, twtr_clk;
  122. unsigned int sdram_type;
  123. unsigned int memsize;
  124. unsigned int law_size;
  125. unsigned char caslat, caslat_ctrl;
  126. unsigned int trfc, trfc_clk, trfc_low;
  127. unsigned int trcd_clk, trtp_clk;
  128. unsigned char cke_min_clk;
  129. unsigned char add_lat, wr_lat;
  130. unsigned char wr_data_delay;
  131. unsigned char four_act;
  132. unsigned char cpo;
  133. unsigned char burstlen;
  134. unsigned char odt_cfg, mode_odt_enable;
  135. unsigned int max_bus_clk;
  136. unsigned int max_data_rate, effective_data_rate;
  137. unsigned int ddrc_clk;
  138. unsigned int refresh_clk;
  139. unsigned int sdram_cfg;
  140. unsigned int ddrc_ecc_enable;
  141. unsigned int pvr = get_pvr();
  142. /*
  143. * First disable the memory controller (could be enabled
  144. * by the debugger)
  145. */
  146. clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
  147. sync();
  148. isync();
  149. /* Read SPD parameters with I2C */
  150. CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
  151. SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
  152. #ifdef SPD_DEBUG
  153. spd_debug(&spd);
  154. #endif
  155. /* Check the memory type */
  156. if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
  157. debug("DDR: Module mem type is %02X\n", spd.mem_type);
  158. return 0;
  159. }
  160. /* Check the number of physical bank */
  161. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  162. n_ranks = spd.nrows;
  163. } else {
  164. n_ranks = (spd.nrows & 0x7) + 1;
  165. }
  166. if (n_ranks > 2) {
  167. printf("DDR: The number of physical bank is %02X\n", n_ranks);
  168. return 0;
  169. }
  170. /* Check if the number of row of the module is in the range of DDRC */
  171. if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
  172. printf("DDR: Row number is out of range of DDRC, row=%02X\n",
  173. spd.nrow_addr);
  174. return 0;
  175. }
  176. /* Check if the number of col of the module is in the range of DDRC */
  177. if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
  178. printf("DDR: Col number is out of range of DDRC, col=%02X\n",
  179. spd.ncol_addr);
  180. return 0;
  181. }
  182. #ifdef CONFIG_SYS_DDRCDR_VALUE
  183. /*
  184. * Adjust DDR II IO voltage biasing. It just makes it work.
  185. */
  186. if(spd.mem_type == SPD_MEMTYPE_DDR2) {
  187. immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  188. }
  189. udelay(50000);
  190. #endif
  191. /*
  192. * ODT configuration recommendation from DDR Controller Chapter.
  193. */
  194. odt_rd_cfg = 0; /* Never assert ODT */
  195. odt_wr_cfg = 0; /* Never assert ODT */
  196. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  197. odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
  198. }
  199. /* Setup DDR chip select register */
  200. #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
  201. ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  202. ddr->cs_config[0] = ( 1 << 31
  203. | (odt_rd_cfg << 20)
  204. | (odt_wr_cfg << 16)
  205. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  206. | ((spd.nrow_addr - 12) << 8)
  207. | (spd.ncol_addr - 8) );
  208. debug("\n");
  209. debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
  210. debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
  211. if (n_ranks == 2) {
  212. ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
  213. | ((banksize(spd.row_dens) >> 23) - 1) );
  214. ddr->cs_config[1] = ( 1<<31
  215. | (odt_rd_cfg << 20)
  216. | (odt_wr_cfg << 16)
  217. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  218. | ((spd.nrow_addr - 12) << 8)
  219. | (spd.ncol_addr - 8) );
  220. debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
  221. debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
  222. }
  223. #else
  224. ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  225. ddr->cs_config[2] = ( 1 << 31
  226. | (odt_rd_cfg << 20)
  227. | (odt_wr_cfg << 16)
  228. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  229. | ((spd.nrow_addr - 12) << 8)
  230. | (spd.ncol_addr - 8) );
  231. debug("\n");
  232. debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
  233. debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
  234. if (n_ranks == 2) {
  235. ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
  236. | ((banksize(spd.row_dens) >> 23) - 1) );
  237. ddr->cs_config[3] = ( 1<<31
  238. | (odt_rd_cfg << 20)
  239. | (odt_wr_cfg << 16)
  240. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  241. | ((spd.nrow_addr - 12) << 8)
  242. | (spd.ncol_addr - 8) );
  243. debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
  244. debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
  245. }
  246. #endif
  247. /*
  248. * Figure out memory size in Megabytes.
  249. */
  250. memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
  251. /*
  252. * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
  253. */
  254. law_size = 19 + __ilog2(memsize);
  255. /*
  256. * Set up LAWBAR for all of DDR.
  257. */
  258. ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  259. ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
  260. debug("DDR:bar=0x%08x\n", ecm->bar);
  261. debug("DDR:ar=0x%08x\n", ecm->ar);
  262. /*
  263. * Find the largest CAS by locating the highest 1 bit
  264. * in the spd.cas_lat field. Translate it to a DDR
  265. * controller field value:
  266. *
  267. * CAS Lat DDR I DDR II Ctrl
  268. * Clocks SPD Bit SPD Bit Value
  269. * ------- ------- ------- -----
  270. * 1.0 0 0001
  271. * 1.5 1 0010
  272. * 2.0 2 2 0011
  273. * 2.5 3 0100
  274. * 3.0 4 3 0101
  275. * 3.5 5 0110
  276. * 4.0 6 4 0111
  277. * 4.5 1000
  278. * 5.0 5 1001
  279. */
  280. caslat = __ilog2(spd.cas_lat);
  281. if ((spd.mem_type == SPD_MEMTYPE_DDR)
  282. && (caslat > 6)) {
  283. printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
  284. return 0;
  285. } else if (spd.mem_type == SPD_MEMTYPE_DDR2
  286. && (caslat < 2 || caslat > 5)) {
  287. printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
  288. spd.cas_lat);
  289. return 0;
  290. }
  291. debug("DDR: caslat SPD bit is %d\n", caslat);
  292. max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
  293. + (spd.clk_cycle & 0x0f));
  294. max_data_rate = max_bus_clk * 2;
  295. debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
  296. ddrc_clk = gd->mem_clk / 1000000;
  297. effective_data_rate = 0;
  298. if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
  299. if (spd.cas_lat & 0x08)
  300. caslat = 3;
  301. else
  302. caslat = 4;
  303. if (ddrc_clk <= 460 && ddrc_clk > 350)
  304. effective_data_rate = 400;
  305. else if (ddrc_clk <=350 && ddrc_clk > 280)
  306. effective_data_rate = 333;
  307. else if (ddrc_clk <= 280 && ddrc_clk > 230)
  308. effective_data_rate = 266;
  309. else
  310. effective_data_rate = 200;
  311. } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
  312. if (ddrc_clk <= 460 && ddrc_clk > 350) {
  313. /* DDR controller clk at 350~460 */
  314. effective_data_rate = 400; /* 5ns */
  315. caslat = caslat;
  316. } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
  317. /* DDR controller clk at 280~350 */
  318. effective_data_rate = 333; /* 6ns */
  319. if (spd.clk_cycle2 == 0x60)
  320. caslat = caslat - 1;
  321. else
  322. caslat = caslat;
  323. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  324. /* DDR controller clk at 230~280 */
  325. effective_data_rate = 266; /* 7.5ns */
  326. if (spd.clk_cycle3 == 0x75)
  327. caslat = caslat - 2;
  328. else if (spd.clk_cycle2 == 0x75)
  329. caslat = caslat - 1;
  330. else
  331. caslat = caslat;
  332. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  333. /* DDR controller clk at 90~230 */
  334. effective_data_rate = 200; /* 10ns */
  335. if (spd.clk_cycle3 == 0xa0)
  336. caslat = caslat - 2;
  337. else if (spd.clk_cycle2 == 0xa0)
  338. caslat = caslat - 1;
  339. else
  340. caslat = caslat;
  341. }
  342. } else if (max_data_rate >= 323) { /* it is DDR 333 */
  343. if (ddrc_clk <= 350 && ddrc_clk > 280) {
  344. /* DDR controller clk at 280~350 */
  345. effective_data_rate = 333; /* 6ns */
  346. caslat = caslat;
  347. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  348. /* DDR controller clk at 230~280 */
  349. effective_data_rate = 266; /* 7.5ns */
  350. if (spd.clk_cycle2 == 0x75)
  351. caslat = caslat - 1;
  352. else
  353. caslat = caslat;
  354. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  355. /* DDR controller clk at 90~230 */
  356. effective_data_rate = 200; /* 10ns */
  357. if (spd.clk_cycle3 == 0xa0)
  358. caslat = caslat - 2;
  359. else if (spd.clk_cycle2 == 0xa0)
  360. caslat = caslat - 1;
  361. else
  362. caslat = caslat;
  363. }
  364. } else if (max_data_rate >= 256) { /* it is DDR 266 */
  365. if (ddrc_clk <= 350 && ddrc_clk > 280) {
  366. /* DDR controller clk at 280~350 */
  367. printf("DDR: DDR controller freq is more than "
  368. "max data rate of the module\n");
  369. return 0;
  370. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  371. /* DDR controller clk at 230~280 */
  372. effective_data_rate = 266; /* 7.5ns */
  373. caslat = caslat;
  374. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  375. /* DDR controller clk at 90~230 */
  376. effective_data_rate = 200; /* 10ns */
  377. if (spd.clk_cycle2 == 0xa0)
  378. caslat = caslat - 1;
  379. }
  380. } else if (max_data_rate >= 190) { /* it is DDR 200 */
  381. if (ddrc_clk <= 350 && ddrc_clk > 230) {
  382. /* DDR controller clk at 230~350 */
  383. printf("DDR: DDR controller freq is more than "
  384. "max data rate of the module\n");
  385. return 0;
  386. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  387. /* DDR controller clk at 90~230 */
  388. effective_data_rate = 200; /* 10ns */
  389. caslat = caslat;
  390. }
  391. }
  392. debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
  393. debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
  394. /*
  395. * Errata DDR6 work around: input enable 2 cycles earlier.
  396. * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
  397. */
  398. if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
  399. if (caslat == 2)
  400. ddr->debug_reg = 0x201c0000; /* CL=2 */
  401. else if (caslat == 3)
  402. ddr->debug_reg = 0x202c0000; /* CL=2.5 */
  403. else if (caslat == 4)
  404. ddr->debug_reg = 0x202c0000; /* CL=3.0 */
  405. sync();
  406. debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
  407. }
  408. /*
  409. * Convert caslat clocks to DDR controller value.
  410. * Force caslat_ctrl to be DDR Controller field-sized.
  411. */
  412. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  413. caslat_ctrl = (caslat + 1) & 0x07;
  414. } else {
  415. caslat_ctrl = (2 * caslat - 1) & 0x0f;
  416. }
  417. debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
  418. debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
  419. caslat, caslat_ctrl);
  420. /*
  421. * Timing Config 0.
  422. * Avoid writing for DDR I.
  423. */
  424. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  425. unsigned char taxpd_clk = 8; /* By the book. */
  426. unsigned char tmrd_clk = 2; /* By the book. */
  427. unsigned char act_pd_exit = 2; /* Empirical? */
  428. unsigned char pre_pd_exit = 6; /* Empirical? */
  429. ddr->timing_cfg_0 = (0
  430. | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
  431. | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
  432. | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
  433. | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
  434. );
  435. debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
  436. }
  437. /*
  438. * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
  439. * use conservative value.
  440. * For DDR II, they are bytes 36 and 37, in quarter nanos.
  441. */
  442. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  443. twr_clk = 3; /* Clocks */
  444. twtr_clk = 1; /* Clocks */
  445. } else {
  446. twr_clk = picos_to_clk(spd.twr * 250);
  447. twtr_clk = picos_to_clk(spd.twtr * 250);
  448. if (twtr_clk < 2)
  449. twtr_clk = 2;
  450. }
  451. /*
  452. * Calculate Trfc, in picos.
  453. * DDR I: Byte 42 straight up in ns.
  454. * DDR II: Byte 40 and 42 swizzled some, in ns.
  455. */
  456. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  457. trfc = spd.trfc * 1000; /* up to ps */
  458. } else {
  459. unsigned int byte40_table_ps[8] = {
  460. 0,
  461. 250,
  462. 330,
  463. 500,
  464. 660,
  465. 750,
  466. 0,
  467. 0
  468. };
  469. trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
  470. + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
  471. }
  472. trfc_clk = picos_to_clk(trfc);
  473. /*
  474. * Trcd, Byte 29, from quarter nanos to ps and clocks.
  475. */
  476. trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
  477. /*
  478. * Convert trfc_clk to DDR controller fields. DDR I should
  479. * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
  480. * 83xx controller has an extended REFREC field of three bits.
  481. * The controller automatically adds 8 clocks to this value,
  482. * so preadjust it down 8 first before splitting it up.
  483. */
  484. trfc_low = (trfc_clk - 8) & 0xf;
  485. ddr->timing_cfg_1 =
  486. (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
  487. ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
  488. (trcd_clk << 20 ) | /* ACTTORW */
  489. (caslat_ctrl << 16 ) | /* CASLAT */
  490. (trfc_low << 12 ) | /* REFEC */
  491. ((twr_clk & 0x07) << 8) | /* WRRREC */
  492. ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
  493. ((twtr_clk & 0x07) << 0) /* WRTORD */
  494. );
  495. /*
  496. * Additive Latency
  497. * For DDR I, 0.
  498. * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
  499. * which comes from Trcd, and also note that:
  500. * add_lat + caslat must be >= 4
  501. */
  502. add_lat = 0;
  503. if (spd.mem_type == SPD_MEMTYPE_DDR2
  504. && (odt_wr_cfg || odt_rd_cfg)
  505. && (caslat < 4)) {
  506. add_lat = 4 - caslat;
  507. if ((add_lat + caslat) < 4) {
  508. add_lat = 0;
  509. }
  510. }
  511. /*
  512. * Write Data Delay
  513. * Historically 0x2 == 4/8 clock delay.
  514. * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
  515. */
  516. wr_data_delay = 2;
  517. #ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
  518. wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
  519. #endif
  520. /*
  521. * Write Latency
  522. * Read to Precharge
  523. * Minimum CKE Pulse Width.
  524. * Four Activate Window
  525. */
  526. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  527. /*
  528. * This is a lie. It should really be 1, but if it is
  529. * set to 1, bits overlap into the old controller's
  530. * otherwise unused ACSM field. If we leave it 0, then
  531. * the HW will magically treat it as 1 for DDR 1. Oh Yea.
  532. */
  533. wr_lat = 0;
  534. trtp_clk = 2; /* By the book. */
  535. cke_min_clk = 1; /* By the book. */
  536. four_act = 1; /* By the book. */
  537. } else {
  538. wr_lat = caslat - 1;
  539. /* Convert SPD value from quarter nanos to picos. */
  540. trtp_clk = picos_to_clk(spd.trtp * 250);
  541. if (trtp_clk < 2)
  542. trtp_clk = 2;
  543. trtp_clk += add_lat;
  544. cke_min_clk = 3; /* By the book. */
  545. four_act = picos_to_clk(37500); /* By the book. 1k pages? */
  546. }
  547. /*
  548. * Empirically set ~MCAS-to-preamble override for DDR 2.
  549. * Your mileage will vary.
  550. */
  551. cpo = 0;
  552. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  553. #ifdef CONFIG_SYS_DDR_CPO
  554. cpo = CONFIG_SYS_DDR_CPO;
  555. #else
  556. if (effective_data_rate == 266) {
  557. cpo = 0x4; /* READ_LAT + 1/2 */
  558. } else if (effective_data_rate == 333) {
  559. cpo = 0x6; /* READ_LAT + 1 */
  560. } else if (effective_data_rate == 400) {
  561. cpo = 0x7; /* READ_LAT + 5/4 */
  562. } else {
  563. /* Automatic calibration */
  564. cpo = 0x1f;
  565. }
  566. #endif
  567. }
  568. ddr->timing_cfg_2 = (0
  569. | ((add_lat & 0x7) << 28) /* ADD_LAT */
  570. | ((cpo & 0x1f) << 23) /* CPO */
  571. | ((wr_lat & 0x7) << 19) /* WR_LAT */
  572. | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
  573. | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
  574. | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
  575. | ((four_act & 0x1f) << 0) /* FOUR_ACT */
  576. );
  577. debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
  578. debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
  579. /* Check DIMM data bus width */
  580. if (spd.dataw_lsb < 64) {
  581. if (spd.mem_type == SPD_MEMTYPE_DDR)
  582. burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
  583. else
  584. burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
  585. debug("\n DDR DIMM: data bus width is 32 bit");
  586. } else {
  587. burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
  588. debug("\n DDR DIMM: data bus width is 64 bit");
  589. }
  590. /* Is this an ECC DDR chip? */
  591. if (spd.config == 0x02)
  592. debug(" with ECC\n");
  593. else
  594. debug(" without ECC\n");
  595. /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
  596. Burst type is sequential
  597. */
  598. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  599. switch (caslat) {
  600. case 1:
  601. ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
  602. break;
  603. case 2:
  604. ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
  605. break;
  606. case 3:
  607. ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
  608. break;
  609. case 4:
  610. ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
  611. break;
  612. default:
  613. printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
  614. return 0;
  615. }
  616. } else {
  617. mode_odt_enable = 0x0; /* Default disabled */
  618. if (odt_wr_cfg || odt_rd_cfg) {
  619. /*
  620. * Bits 6 and 2 in Extended MRS(1)
  621. * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
  622. * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
  623. */
  624. mode_odt_enable = 0x40; /* 150 Ohm */
  625. }
  626. ddr->sdram_mode =
  627. (0
  628. | (1 << (16 + 10)) /* DQS Differential disable */
  629. #ifdef CONFIG_SYS_DDR_MODE_WEAK
  630. | (1 << (16 + 1)) /* weak driver (~60%) */
  631. #endif
  632. | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
  633. | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
  634. | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
  635. | (caslat << 4) /* caslat */
  636. | (burstlen << 0) /* Burst length */
  637. );
  638. }
  639. debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
  640. /*
  641. * Clear EMRS2 and EMRS3.
  642. */
  643. ddr->sdram_mode2 = 0;
  644. debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
  645. switch (spd.refresh) {
  646. case 0x00:
  647. case 0x80:
  648. refresh_clk = picos_to_clk(15625000);
  649. break;
  650. case 0x01:
  651. case 0x81:
  652. refresh_clk = picos_to_clk(3900000);
  653. break;
  654. case 0x02:
  655. case 0x82:
  656. refresh_clk = picos_to_clk(7800000);
  657. break;
  658. case 0x03:
  659. case 0x83:
  660. refresh_clk = picos_to_clk(31300000);
  661. break;
  662. case 0x04:
  663. case 0x84:
  664. refresh_clk = picos_to_clk(62500000);
  665. break;
  666. case 0x05:
  667. case 0x85:
  668. refresh_clk = picos_to_clk(125000000);
  669. break;
  670. default:
  671. refresh_clk = 0x512;
  672. break;
  673. }
  674. /*
  675. * Set BSTOPRE to 0x100 for page mode
  676. * If auto-charge is used, set BSTOPRE = 0
  677. */
  678. ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
  679. debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
  680. /*
  681. * SDRAM Cfg 2
  682. */
  683. odt_cfg = 0;
  684. #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
  685. if (odt_rd_cfg | odt_wr_cfg) {
  686. odt_cfg = 0x2; /* ODT to IOs during reads */
  687. }
  688. #endif
  689. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  690. ddr->sdram_cfg2 = (0
  691. | (0 << 26) /* True DQS */
  692. | (odt_cfg << 21) /* ODT only read */
  693. | (1 << 12) /* 1 refresh at a time */
  694. );
  695. debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
  696. }
  697. #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
  698. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  699. #endif
  700. debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
  701. sync();
  702. isync();
  703. udelay(600);
  704. /*
  705. * Figure out the settings for the sdram_cfg register. Build up
  706. * the value in 'sdram_cfg' before writing since the write into
  707. * the register will actually enable the memory controller, and all
  708. * settings must be done before enabling.
  709. *
  710. * sdram_cfg[0] = 1 (ddr sdram logic enable)
  711. * sdram_cfg[1] = 1 (self-refresh-enable)
  712. * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
  713. * 010 DDR 1 SDRAM
  714. * 011 DDR 2 SDRAM
  715. * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
  716. * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
  717. */
  718. if (spd.mem_type == SPD_MEMTYPE_DDR)
  719. sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
  720. else
  721. sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
  722. sdram_cfg = (0
  723. | SDRAM_CFG_MEM_EN /* DDR enable */
  724. | SDRAM_CFG_SREN /* Self refresh */
  725. | sdram_type /* SDRAM type */
  726. );
  727. /* sdram_cfg[3] = RD_EN - registered DIMM enable */
  728. if (spd.mod_attr & 0x02)
  729. sdram_cfg |= SDRAM_CFG_RD_EN;
  730. /* The DIMM is 32bit width */
  731. if (spd.dataw_lsb < 64) {
  732. if (spd.mem_type == SPD_MEMTYPE_DDR)
  733. sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
  734. if (spd.mem_type == SPD_MEMTYPE_DDR2)
  735. sdram_cfg |= SDRAM_CFG_32_BE;
  736. }
  737. ddrc_ecc_enable = 0;
  738. #if defined(CONFIG_DDR_ECC)
  739. /* Enable ECC with sdram_cfg[2] */
  740. if (spd.config == 0x02) {
  741. sdram_cfg |= 0x20000000;
  742. ddrc_ecc_enable = 1;
  743. /* disable error detection */
  744. ddr->err_disable = ~ECC_ERROR_ENABLE;
  745. /* set single bit error threshold to maximum value,
  746. * reset counter to zero */
  747. ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
  748. (0 << ECC_ERROR_MAN_SBEC_SHIFT);
  749. }
  750. debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
  751. debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
  752. #endif
  753. debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
  754. #if defined(CONFIG_DDR_2T_TIMING)
  755. /*
  756. * Enable 2T timing by setting sdram_cfg[16].
  757. */
  758. sdram_cfg |= SDRAM_CFG_2T_EN;
  759. #endif
  760. /* Enable controller, and GO! */
  761. ddr->sdram_cfg = sdram_cfg;
  762. sync();
  763. isync();
  764. udelay(500);
  765. debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
  766. return memsize; /*in MBytes*/
  767. }
  768. #endif /* CONFIG_SPD_EEPROM */
  769. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  770. static inline u32 mftbu(void)
  771. {
  772. u32 rval;
  773. asm volatile("mftbu %0" : "=r" (rval));
  774. return rval;
  775. }
  776. static inline u32 mftb(void)
  777. {
  778. u32 rval;
  779. asm volatile("mftb %0" : "=r" (rval));
  780. return rval;
  781. }
  782. /*
  783. * Use timebase counter, get_timer() is not available
  784. * at this point of initialization yet.
  785. */
  786. static __inline__ unsigned long get_tbms (void)
  787. {
  788. unsigned long tbl;
  789. unsigned long tbu1, tbu2;
  790. unsigned long ms;
  791. unsigned long long tmp;
  792. ulong tbclk = get_tbclk();
  793. /* get the timebase ticks */
  794. do {
  795. tbu1 = mftbu();
  796. tbl = mftb();
  797. tbu2 = mftbu();
  798. } while (tbu1 != tbu2);
  799. /* convert ticks to ms */
  800. tmp = (unsigned long long)(tbu1);
  801. tmp = (tmp << 32);
  802. tmp += (unsigned long long)(tbl);
  803. ms = tmp/(tbclk/1000);
  804. return ms;
  805. }
  806. /*
  807. * Initialize all of memory for ECC, then enable errors.
  808. */
  809. void ddr_enable_ecc(unsigned int dram_size)
  810. {
  811. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  812. volatile ddr83xx_t *ddr= &immap->ddr;
  813. unsigned long t_start, t_end;
  814. register u64 *p;
  815. register uint size;
  816. unsigned int pattern[2];
  817. icache_enable();
  818. t_start = get_tbms();
  819. pattern[0] = 0xdeadbeef;
  820. pattern[1] = 0xdeadbeef;
  821. #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
  822. dma_meminit(pattern[0], dram_size);
  823. #else
  824. debug("ddr init: CPU FP write method\n");
  825. size = dram_size;
  826. for (p = 0; p < (u64*)(size); p++) {
  827. ppcDWstore((u32*)p, pattern);
  828. }
  829. sync();
  830. #endif
  831. t_end = get_tbms();
  832. icache_disable();
  833. debug("\nREADY!!\n");
  834. debug("ddr init duration: %ld ms\n", t_end - t_start);
  835. /* Clear All ECC Errors */
  836. if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
  837. ddr->err_detect |= ECC_ERROR_DETECT_MME;
  838. if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
  839. ddr->err_detect |= ECC_ERROR_DETECT_MBE;
  840. if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
  841. ddr->err_detect |= ECC_ERROR_DETECT_SBE;
  842. if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
  843. ddr->err_detect |= ECC_ERROR_DETECT_MSE;
  844. /* Disable ECC-Interrupts */
  845. ddr->err_int_en &= ECC_ERR_INT_DISABLE;
  846. /* Enable errors for ECC */
  847. ddr->err_disable &= ECC_ERROR_ENABLE;
  848. sync();
  849. isync();
  850. }
  851. #endif /* CONFIG_DDR_ECC */
  852. #endif /* !CONFIG_MPC83XX_SDRAM */