serdes.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale SerDes initialization routine
  4. *
  5. * Copyright 2007,2011 Freescale Semiconductor, Inc.
  6. * Copyright (C) 2008 MontaVista Software, Inc.
  7. *
  8. * Author: Li Yang <leoli@freescale.com>
  9. */
  10. #ifndef CONFIG_MPC83XX_SERDES
  11. #include <config.h>
  12. #include <common.h>
  13. #include <asm/io.h>
  14. #include <asm/fsl_mpc83xx_serdes.h>
  15. #include <linux/delay.h>
  16. /* SerDes registers */
  17. #define FSL_SRDSCR0_OFFS 0x0
  18. #define FSL_SRDSCR0_DPP_1V2 0x00008800
  19. #define FSL_SRDSCR0_TXEQA_MASK 0x00007000
  20. #define FSL_SRDSCR0_TXEQA_SATA 0x00001000
  21. #define FSL_SRDSCR0_TXEQE_MASK 0x00000700
  22. #define FSL_SRDSCR0_TXEQE_SATA 0x00000100
  23. #define FSL_SRDSCR1_OFFS 0x4
  24. #define FSL_SRDSCR1_PLLBW 0x00000040
  25. #define FSL_SRDSCR2_OFFS 0x8
  26. #define FSL_SRDSCR2_VDD_1V2 0x00800000
  27. #define FSL_SRDSCR2_SEIC_MASK 0x00001c1c
  28. #define FSL_SRDSCR2_SEIC_SATA 0x00001414
  29. #define FSL_SRDSCR2_SEIC_PEX 0x00001010
  30. #define FSL_SRDSCR2_SEIC_SGMII 0x00000101
  31. #define FSL_SRDSCR3_OFFS 0xc
  32. #define FSL_SRDSCR3_KFR_SATA 0x10100000
  33. #define FSL_SRDSCR3_KPH_SATA 0x04040000
  34. #define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000
  35. #define FSL_SRDSCR3_SDTXL_SATA 0x00000505
  36. #define FSL_SRDSCR4_OFFS 0x10
  37. #define FSL_SRDSCR4_PROT_SATA 0x00000808
  38. #define FSL_SRDSCR4_PROT_PEX 0x00000101
  39. #define FSL_SRDSCR4_PROT_SGMII 0x00000505
  40. #define FSL_SRDSCR4_PLANE_X2 0x01000000
  41. #define FSL_SRDSRSTCTL_OFFS 0x20
  42. #define FSL_SRDSRSTCTL_RST 0x80000000
  43. #define FSL_SRDSRSTCTL_SATA_RESET 0xf
  44. void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
  45. {
  46. void *regs = (void *)CONFIG_SYS_IMMR + offset;
  47. u32 tmp;
  48. /* 1.0V corevdd */
  49. if (vdd) {
  50. /* DPPE/DPPA = 0 */
  51. tmp = in_be32(regs + FSL_SRDSCR0_OFFS);
  52. tmp &= ~FSL_SRDSCR0_DPP_1V2;
  53. out_be32(regs + FSL_SRDSCR0_OFFS, tmp);
  54. /* VDD = 0 */
  55. tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
  56. tmp &= ~FSL_SRDSCR2_VDD_1V2;
  57. out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
  58. }
  59. /* protocol specific configuration */
  60. switch (proto) {
  61. case FSL_SERDES_PROTO_SATA:
  62. /* Set and clear reset bits */
  63. tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
  64. tmp |= FSL_SRDSRSTCTL_SATA_RESET;
  65. out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
  66. udelay(1000);
  67. tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
  68. out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
  69. /* Configure SRDSCR0 */
  70. clrsetbits_be32(regs + FSL_SRDSCR0_OFFS,
  71. FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK,
  72. FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA);
  73. /* Configure SRDSCR1 */
  74. tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
  75. tmp &= ~FSL_SRDSCR1_PLLBW;
  76. out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
  77. /* Configure SRDSCR2 */
  78. tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
  79. tmp &= ~FSL_SRDSCR2_SEIC_MASK;
  80. tmp |= FSL_SRDSCR2_SEIC_SATA;
  81. out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
  82. /* Configure SRDSCR3 */
  83. tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |
  84. FSL_SRDSCR3_SDFM_SATA_PEX |
  85. FSL_SRDSCR3_SDTXL_SATA;
  86. out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
  87. /* Configure SRDSCR4 */
  88. tmp = rfcks | FSL_SRDSCR4_PROT_SATA;
  89. out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
  90. break;
  91. case FSL_SERDES_PROTO_PEX:
  92. case FSL_SERDES_PROTO_PEX_X2:
  93. /* Configure SRDSCR1 */
  94. tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
  95. tmp |= FSL_SRDSCR1_PLLBW;
  96. out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
  97. /* Configure SRDSCR2 */
  98. tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
  99. tmp &= ~FSL_SRDSCR2_SEIC_MASK;
  100. tmp |= FSL_SRDSCR2_SEIC_PEX;
  101. out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
  102. /* Configure SRDSCR3 */
  103. tmp = FSL_SRDSCR3_SDFM_SATA_PEX;
  104. out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
  105. /* Configure SRDSCR4 */
  106. tmp = rfcks | FSL_SRDSCR4_PROT_PEX;
  107. if (proto == FSL_SERDES_PROTO_PEX_X2)
  108. tmp |= FSL_SRDSCR4_PLANE_X2;
  109. out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
  110. break;
  111. case FSL_SERDES_PROTO_SGMII:
  112. /* Configure SRDSCR1 */
  113. tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
  114. tmp &= ~FSL_SRDSCR1_PLLBW;
  115. out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
  116. /* Configure SRDSCR2 */
  117. tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
  118. tmp &= ~FSL_SRDSCR2_SEIC_MASK;
  119. tmp |= FSL_SRDSCR2_SEIC_SGMII;
  120. out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
  121. /* Configure SRDSCR3 */
  122. out_be32(regs + FSL_SRDSCR3_OFFS, 0);
  123. /* Configure SRDSCR4 */
  124. tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;
  125. out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
  126. break;
  127. default:
  128. return;
  129. }
  130. /* Do a software reset */
  131. tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
  132. tmp |= FSL_SRDSRSTCTL_RST;
  133. out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
  134. }
  135. #endif /* !CONFIG_MPC83XX_SERDES */