pcie.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2008-2009 MontaVista Software, Inc.
  5. *
  6. * Authors: Tony Li <tony.li@freescale.com>
  7. * Anton Vorontsov <avorontsov@ru.mvista.com>
  8. */
  9. #include <common.h>
  10. #include <pci.h>
  11. #include <mpc83xx.h>
  12. #include <asm/io.h>
  13. #include <linux/delay.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #define PCIE_MAX_BUSES 2
  16. static struct {
  17. u32 base;
  18. u32 size;
  19. } mpc83xx_pcie_cfg_space[] = {
  20. {
  21. .base = CONFIG_SYS_PCIE1_CFG_BASE,
  22. .size = CONFIG_SYS_PCIE1_CFG_SIZE,
  23. },
  24. #if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
  25. {
  26. .base = CONFIG_SYS_PCIE2_CFG_BASE,
  27. .size = CONFIG_SYS_PCIE2_CFG_SIZE,
  28. },
  29. #endif
  30. };
  31. #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
  32. /* private structure for mpc83xx pcie hose */
  33. static struct mpc83xx_pcie_priv {
  34. u8 index;
  35. } pcie_priv[PCIE_MAX_BUSES] = {
  36. {
  37. /* pcie controller 1 */
  38. .index = 0,
  39. },
  40. {
  41. /* pcie controller 2 */
  42. .index = 1,
  43. },
  44. };
  45. static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
  46. {
  47. int bus = PCI_BUS(dev) - hose->first_busno;
  48. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  49. struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
  50. pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
  51. struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
  52. u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
  53. u32 dev_base = bus << 24 | devfn << 16;
  54. if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
  55. return -1;
  56. /*
  57. * Workaround for the HW bug: for Type 0 configure transactions the
  58. * PCI-E controller does not check the device number bits and just
  59. * assumes that the device number bits are 0.
  60. */
  61. if (devfn & 0xf8)
  62. return -1;
  63. out_le32(&out_win->tarl, dev_base);
  64. return 0;
  65. }
  66. #define cfg_read(val, addr, type, op) \
  67. do { *val = op((type)(addr)); } while (0)
  68. #define cfg_write(val, addr, type, op) \
  69. do { op((type *)(addr), (val)); } while (0)
  70. #define cfg_read_err(val) do { *val = -1; } while (0)
  71. #define cfg_write_err(val) do { } while (0)
  72. #define PCIE_OP(rw, size, type, op) \
  73. static int pcie_##rw##_config_##size(struct pci_controller *hose, \
  74. pci_dev_t dev, int offset, \
  75. type val) \
  76. { \
  77. int ret; \
  78. \
  79. ret = mpc83xx_pcie_remap_cfg(hose, dev); \
  80. if (ret) { \
  81. cfg_##rw##_err(val); \
  82. return ret; \
  83. } \
  84. cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
  85. return 0; \
  86. }
  87. PCIE_OP(read, byte, u8 *, in_8)
  88. PCIE_OP(read, word, u16 *, in_le16)
  89. PCIE_OP(read, dword, u32 *, in_le32)
  90. PCIE_OP(write, byte, u8, out_8)
  91. PCIE_OP(write, word, u16, out_le16)
  92. PCIE_OP(write, dword, u32, out_le32)
  93. static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
  94. u8 link)
  95. {
  96. extern void disable_addr_trans(void); /* start.S */
  97. static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
  98. struct pci_controller *hose = &pcie_hose[bus];
  99. int i;
  100. /*
  101. * There are no spare BATs to remap all PCI-E windows for U-Boot, so
  102. * disable translations. In general, this is not great solution, and
  103. * that's why we don't register PCI-E hoses by default.
  104. */
  105. disable_addr_trans();
  106. for (i = 0; i < 2; i++, reg++) {
  107. if (reg->size == 0)
  108. break;
  109. hose->regions[i] = *reg;
  110. hose->region_count++;
  111. }
  112. i = hose->region_count++;
  113. hose->regions[i].bus_start = 0;
  114. hose->regions[i].phys_start = 0;
  115. hose->regions[i].size = gd->ram_size;
  116. hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
  117. i = hose->region_count++;
  118. hose->regions[i].bus_start = CONFIG_SYS_IMMR;
  119. hose->regions[i].phys_start = CONFIG_SYS_IMMR;
  120. hose->regions[i].size = 0x100000;
  121. hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
  122. hose->first_busno = pci_last_busno() + 1;
  123. hose->last_busno = 0xff;
  124. hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
  125. hose->priv_data = &pcie_priv[bus];
  126. pci_set_ops(hose,
  127. pcie_read_config_byte,
  128. pcie_read_config_word,
  129. pcie_read_config_dword,
  130. pcie_write_config_byte,
  131. pcie_write_config_word,
  132. pcie_write_config_dword);
  133. if (!link)
  134. hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
  135. pci_register_hose(hose);
  136. #ifdef CONFIG_PCI_SCAN_SHOW
  137. printf("PCI: Bus Dev VenId DevId Class Int\n");
  138. #endif
  139. /*
  140. * Hose scan.
  141. */
  142. hose->last_busno = pci_hose_scan(hose);
  143. }
  144. #else
  145. static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
  146. u8 link) {}
  147. #endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
  148. int get_pcie_clk(int index)
  149. {
  150. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  151. u32 pci_sync_in;
  152. u8 spmf;
  153. u8 clkin_div;
  154. u32 sccr;
  155. u32 csb_clk;
  156. u32 testval;
  157. clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
  158. sccr = im->clk.sccr;
  159. pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
  160. spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
  161. csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
  162. if (index)
  163. testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT;
  164. else
  165. testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT;
  166. switch (testval) {
  167. case 0:
  168. return 0;
  169. case 1:
  170. return csb_clk;
  171. case 2:
  172. return csb_clk / 2;
  173. case 3:
  174. return csb_clk / 3;
  175. }
  176. return 0;
  177. }
  178. static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
  179. {
  180. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  181. pex83xx_t *pex = &immr->pciexp[bus];
  182. struct pex_outbound_window *out_win;
  183. struct pex_inbound_window *in_win;
  184. void *hose_cfg_base;
  185. unsigned int ram_sz;
  186. unsigned int barl;
  187. unsigned int tar;
  188. u16 reg16;
  189. int i;
  190. /* Enable pex csb bridge inbound & outbound transactions */
  191. out_le32(&pex->bridge.pex_csb_ctrl,
  192. in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
  193. PEX_CSB_CTRL_IBPIOE);
  194. /* Enable bridge outbound */
  195. out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
  196. PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
  197. PEX_CSB_OBCTRL_CFGWE);
  198. out_win = &pex->bridge.pex_outbound_win[0];
  199. out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
  200. mpc83xx_pcie_cfg_space[bus].size);
  201. out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
  202. out_le32(&out_win->tarl, 0);
  203. out_le32(&out_win->tarh, 0);
  204. for (i = 0; i < 2; i++) {
  205. u32 ar;
  206. if (reg[i].size == 0)
  207. break;
  208. out_win = &pex->bridge.pex_outbound_win[i + 1];
  209. out_le32(&out_win->bar, reg[i].phys_start);
  210. out_le32(&out_win->tarl, reg[i].bus_start);
  211. out_le32(&out_win->tarh, 0);
  212. ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
  213. if (reg[i].flags & PCI_REGION_IO)
  214. ar |= PEX_OWAR_TYPE_IO;
  215. else
  216. ar |= PEX_OWAR_TYPE_MEM;
  217. out_le32(&out_win->ar, ar);
  218. }
  219. out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
  220. ram_sz = gd->ram_size;
  221. barl = 0;
  222. tar = 0;
  223. i = 0;
  224. while (ram_sz > 0) {
  225. in_win = &pex->bridge.pex_inbound_win[i];
  226. out_le32(&in_win->barl, barl);
  227. out_le32(&in_win->barh, 0x0);
  228. out_le32(&in_win->tar, tar);
  229. if (ram_sz >= 0x10000000) {
  230. /* The maxium windows size is 256M */
  231. out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
  232. PEX_IWAR_TYPE_PF | 0x0FFFF000);
  233. barl += 0x10000000;
  234. tar += 0x10000000;
  235. ram_sz -= 0x10000000;
  236. } else {
  237. /* The UM is not clear here.
  238. * So, round up to even Mb boundary */
  239. ram_sz = ram_sz >> (20 +
  240. ((ram_sz & 0xFFFFF) ? 1 : 0));
  241. if (!(ram_sz % 2))
  242. ram_sz -= 1;
  243. out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
  244. PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
  245. ram_sz = 0;
  246. }
  247. i++;
  248. }
  249. in_win = &pex->bridge.pex_inbound_win[i];
  250. out_le32(&in_win->barl, CONFIG_SYS_IMMR);
  251. out_le32(&in_win->barh, 0);
  252. out_le32(&in_win->tar, CONFIG_SYS_IMMR);
  253. out_le32(&in_win->ar, PEX_IWAR_EN |
  254. PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
  255. /* Enable the host virtual INTX interrupts */
  256. out_le32(&pex->bridge.pex_int_axi_misc_enb,
  257. in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
  258. /* Hose configure header is memory-mapped */
  259. hose_cfg_base = (void *)pex;
  260. /* Configure the PCIE controller core clock ratio */
  261. out_le32(hose_cfg_base + PEX_GCLK_RATIO,
  262. ((get_pcie_clk(bus) / 1000000) * 16) / 333);
  263. udelay(1000000);
  264. /* Do Type 1 bridge configuration */
  265. out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
  266. out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
  267. out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
  268. /*
  269. * Write to Command register
  270. */
  271. reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
  272. reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
  273. PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
  274. out_le16(hose_cfg_base + PCI_COMMAND, reg16);
  275. /*
  276. * Clear non-reserved bits in status register.
  277. */
  278. out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
  279. out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
  280. out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
  281. printf("PCIE%d: ", bus);
  282. #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
  283. #define PCI_LTSSM_L0 0x16 /* L0 state */
  284. reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
  285. if (reg16 >= PCI_LTSSM_L0)
  286. printf("link\n");
  287. else
  288. printf("No link\n");
  289. mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
  290. }
  291. /*
  292. * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
  293. * must have been set to cover all of the requested regions.
  294. */
  295. void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
  296. {
  297. int i;
  298. /*
  299. * Release PCI RST Output signal.
  300. * Power on to RST high must be at least 100 ms as per PCI spec.
  301. * On warm boots only 1 ms is required, but we play it safe.
  302. */
  303. udelay(100000);
  304. if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
  305. printf("Second PCIE host contoller not configured!\n");
  306. num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
  307. }
  308. for (i = 0; i < num_buses; i++)
  309. mpc83xx_pcie_init_bus(i, reg[i]);
  310. }