pci.c 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2007
  4. *
  5. * Author: Scott Wood <scottwood@freescale.com>,
  6. * with some bits from older board-specific PCI initialization.
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <pci.h>
  11. #include <asm/bitops.h>
  12. #include <linux/delay.h>
  13. #if defined(CONFIG_OF_LIBFDT)
  14. #include <linux/libfdt.h>
  15. #include <fdt_support.h>
  16. #endif
  17. #include <asm/mpc8349_pci.h>
  18. #define MAX_BUSES 2
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static struct pci_controller pci_hose[MAX_BUSES];
  21. static int pci_num_buses;
  22. static void pci_init_bus(int bus, struct pci_region *reg)
  23. {
  24. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  25. volatile pot83xx_t *pot = immr->ios.pot;
  26. volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
  27. struct pci_controller *hose = &pci_hose[bus];
  28. u32 dev;
  29. u16 reg16;
  30. int i;
  31. if (bus == 1)
  32. pot += 3;
  33. /* Setup outbound translation windows */
  34. for (i = 0; i < 3; i++, reg++, pot++) {
  35. if (reg->size == 0)
  36. break;
  37. hose->regions[i] = *reg;
  38. hose->region_count++;
  39. pot->potar = reg->bus_start >> 12;
  40. pot->pobar = reg->phys_start >> 12;
  41. pot->pocmr = ~(reg->size - 1) >> 12;
  42. if (reg->flags & PCI_REGION_IO)
  43. pot->pocmr |= POCMR_IO;
  44. #ifdef CONFIG_83XX_PCI_STREAMING
  45. else if (reg->flags & PCI_REGION_PREFETCH)
  46. pot->pocmr |= POCMR_SE;
  47. #endif
  48. if (bus == 1)
  49. pot->pocmr |= POCMR_DST;
  50. pot->pocmr |= POCMR_EN;
  51. }
  52. /* Point inbound translation at RAM */
  53. pci_ctrl->pitar1 = 0;
  54. pci_ctrl->pibar1 = 0;
  55. pci_ctrl->piebar1 = 0;
  56. pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
  57. PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
  58. i = hose->region_count++;
  59. hose->regions[i].bus_start = 0;
  60. hose->regions[i].phys_start = 0;
  61. hose->regions[i].size = gd->ram_size;
  62. hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
  63. hose->first_busno = pci_last_busno() + 1;
  64. hose->last_busno = 0xff;
  65. pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
  66. CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
  67. pci_register_hose(hose);
  68. /*
  69. * Write to Command register
  70. */
  71. reg16 = 0xff;
  72. dev = PCI_BDF(hose->first_busno, 0, 0);
  73. pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
  74. reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  75. pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  76. /*
  77. * Clear non-reserved bits in status register.
  78. */
  79. pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  80. pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  81. pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  82. #ifdef CONFIG_PCI_SCAN_SHOW
  83. printf("PCI: Bus Dev VenId DevId Class Int\n");
  84. #endif
  85. #ifndef CONFIG_PCISLAVE
  86. /*
  87. * Hose scan.
  88. */
  89. hose->last_busno = pci_hose_scan(hose);
  90. #endif
  91. }
  92. /*
  93. * The caller must have already set OCCR, and the PCI_LAW BARs
  94. * must have been set to cover all of the requested regions.
  95. *
  96. * If fewer than three regions are requested, then the region
  97. * list is terminated with a region of size 0.
  98. */
  99. void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
  100. {
  101. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  102. int i;
  103. if (num_buses > MAX_BUSES) {
  104. printf("%d PCI buses requested, %d supported\n",
  105. num_buses, MAX_BUSES);
  106. num_buses = MAX_BUSES;
  107. }
  108. pci_num_buses = num_buses;
  109. /*
  110. * Release PCI RST Output signal.
  111. * Power on to RST high must be at least 100 ms as per PCI spec.
  112. * On warm boots only 1 ms is required, but we play it safe.
  113. */
  114. udelay(100000);
  115. for (i = 0; i < num_buses; i++)
  116. immr->pci_ctrl[i].gcr = 1;
  117. /*
  118. * RST high to first config access must be at least 2^25 cycles
  119. * as per PCI spec. This could be cut in half if we know we're
  120. * running at 66MHz. This could be insufficiently long if we're
  121. * running the PCI bus at significantly less than 33MHz.
  122. */
  123. udelay(1020000);
  124. for (i = 0; i < num_buses; i++)
  125. pci_init_bus(i, reg[i]);
  126. }
  127. #ifdef CONFIG_PCISLAVE
  128. #define PCI_FUNCTION_CONFIG 0x44
  129. #define PCI_FUNCTION_CFG_LOCK 0x20
  130. /*
  131. * Unlock the configuration bit so that the host system can begin booting
  132. *
  133. * This should be used after you have:
  134. * 1) Called mpc83xx_pci_init()
  135. * 2) Set up your inbound translation windows to the appropriate size
  136. */
  137. void mpc83xx_pcislave_unlock(int bus)
  138. {
  139. struct pci_controller *hose = &pci_hose[bus];
  140. u32 dev;
  141. u16 reg16;
  142. /* Unlock configuration lock in PCI function configuration register */
  143. dev = PCI_BDF(hose->first_busno, 0, 0);
  144. pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);
  145. reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
  146. pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
  147. /* The configuration bit is now unlocked, so we can scan the bus */
  148. hose->last_busno = pci_hose_scan(hose);
  149. }
  150. #endif
  151. #if defined(CONFIG_OF_LIBFDT)
  152. void ft_pci_setup(void *blob, struct bd_info *bd)
  153. {
  154. int nodeoffset;
  155. int tmp[2];
  156. const char *path;
  157. if (pci_num_buses < 1)
  158. return;
  159. nodeoffset = fdt_path_offset(blob, "/aliases");
  160. if (nodeoffset >= 0) {
  161. path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
  162. if (path) {
  163. tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
  164. tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
  165. do_fixup_by_path(blob, path, "bus-range",
  166. &tmp, sizeof(tmp), 1);
  167. tmp[0] = cpu_to_be32(gd->pci_clk);
  168. do_fixup_by_path(blob, path, "clock-frequency",
  169. &tmp, sizeof(tmp[0]), 1);
  170. }
  171. if (pci_num_buses < 2)
  172. return;
  173. path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
  174. if (path) {
  175. tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
  176. tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
  177. do_fixup_by_path(blob, path, "bus-range",
  178. &tmp, sizeof(tmp), 1);
  179. tmp[0] = cpu_to_be32(gd->pci_clk);
  180. do_fixup_by_path(blob, path, "clock-frequency",
  181. &tmp, sizeof(tmp[0]), 1);
  182. }
  183. }
  184. }
  185. #endif /* CONFIG_OF_LIBFDT */