cpu_init.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm-offsets.h>
  7. #include <mpc83xx.h>
  8. #include <ioports.h>
  9. #include <asm/io.h>
  10. #include <asm/processor.h>
  11. #ifdef CONFIG_USB_EHCI_FSL
  12. #include <usb/ehci-ci.h>
  13. #endif
  14. #include <linux/delay.h>
  15. #include "lblaw/lblaw.h"
  16. #include "elbc/elbc.h"
  17. #include "sysio/sysio.h"
  18. #include "arbiter/arbiter.h"
  19. #include "initreg/initreg.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #ifdef CONFIG_QE
  22. extern qe_iop_conf_t qe_iop_conf_tab[];
  23. extern void qe_config_iopin(u8 port, u8 pin, int dir,
  24. int open_drain, int assign);
  25. extern void qe_init(uint qe_base);
  26. extern void qe_reset(void);
  27. static void config_qe_ioports(void)
  28. {
  29. u8 port, pin;
  30. int dir, open_drain, assign;
  31. int i;
  32. for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  33. port = qe_iop_conf_tab[i].port;
  34. pin = qe_iop_conf_tab[i].pin;
  35. dir = qe_iop_conf_tab[i].dir;
  36. open_drain = qe_iop_conf_tab[i].open_drain;
  37. assign = qe_iop_conf_tab[i].assign;
  38. qe_config_iopin(port, pin, dir, open_drain, assign);
  39. }
  40. }
  41. #endif
  42. /*
  43. * Breathe some life into the CPU...
  44. *
  45. * Set up the memory map,
  46. * initialize a bunch of registers,
  47. * initialize the UPM's
  48. */
  49. void cpu_init_f (volatile immap_t * im)
  50. {
  51. __be32 sccr_mask =
  52. #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  53. SCCR_ENCCM |
  54. #endif
  55. #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  56. SCCR_PCICM |
  57. #endif
  58. #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
  59. SCCR_PCIEXP1CM |
  60. #endif
  61. #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
  62. SCCR_PCIEXP2CM |
  63. #endif
  64. #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  65. SCCR_TSECCM |
  66. #endif
  67. #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  68. SCCR_TSEC1CM |
  69. #endif
  70. #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  71. SCCR_TSEC2CM |
  72. #endif
  73. #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  74. SCCR_TSEC1ON |
  75. #endif
  76. #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  77. SCCR_TSEC2ON |
  78. #endif
  79. #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  80. SCCR_USBMPHCM |
  81. #endif
  82. #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  83. SCCR_USBDRCM |
  84. #endif
  85. #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  86. SCCR_SATACM |
  87. #endif
  88. 0;
  89. __be32 sccr_val =
  90. #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  91. (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
  92. #endif
  93. #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  94. (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
  95. #endif
  96. #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
  97. (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
  98. #endif
  99. #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
  100. (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
  101. #endif
  102. #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  103. (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
  104. #endif
  105. #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  106. (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
  107. #endif
  108. #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  109. (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
  110. #endif
  111. #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  112. (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
  113. #endif
  114. #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  115. (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
  116. #endif
  117. #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  118. (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
  119. #endif
  120. #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  121. (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
  122. #endif
  123. #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  124. (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
  125. #endif
  126. 0;
  127. /* Pointer is writable since we allocated a register for it */
  128. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  129. /* global data region was cleared in start.S */
  130. /* system performance tweaking */
  131. clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
  132. clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
  133. clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
  134. /* RSR - Reset Status Register - clear all status (4.6.1.3) */
  135. gd->arch.reset_status = __raw_readl(&im->reset.rsr);
  136. __raw_writel(~(RSR_RES), &im->reset.rsr);
  137. /* AER - Arbiter Event Register - store status */
  138. gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
  139. gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
  140. /*
  141. * RMR - Reset Mode Register
  142. * contains checkstop reset enable (4.6.1.4)
  143. */
  144. __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
  145. /* LCRR - Clock Ratio Register (10.3.1.16)
  146. * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
  147. */
  148. clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
  149. __raw_readl(&im->im_lbc.lcrr);
  150. isync();
  151. /* Enable Time Base & Decrementer ( so we will have udelay() )*/
  152. setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
  153. /* System General Purpose Register */
  154. #ifdef CONFIG_SYS_SICRH
  155. #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
  156. /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
  157. __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
  158. &im->sysconf.sicrh);
  159. #else
  160. __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
  161. #endif
  162. #endif
  163. #ifdef CONFIG_SYS_SICRL
  164. __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
  165. #endif
  166. #ifdef CONFIG_SYS_GPR1
  167. __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
  168. #endif
  169. #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
  170. __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
  171. #endif
  172. #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
  173. __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
  174. #endif
  175. #ifdef CONFIG_QE
  176. /* Config QE ioports */
  177. config_qe_ioports();
  178. #endif
  179. /* Set up preliminary BR/OR regs */
  180. init_early_memctl_regs();
  181. /* Local Access window setup */
  182. #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
  183. im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
  184. im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
  185. #else
  186. #error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
  187. #endif
  188. #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
  189. im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
  190. im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
  191. #endif
  192. #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
  193. im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
  194. im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
  195. #endif
  196. #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
  197. im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
  198. im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
  199. #endif
  200. #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
  201. im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
  202. im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
  203. #endif
  204. #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
  205. im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
  206. im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
  207. #endif
  208. #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
  209. im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
  210. im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
  211. #endif
  212. #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
  213. im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
  214. im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
  215. #endif
  216. #ifdef CONFIG_SYS_GPIO1_PRELIM
  217. im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
  218. im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
  219. #endif
  220. #ifdef CONFIG_SYS_GPIO2_PRELIM
  221. im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
  222. im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
  223. #endif
  224. #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
  225. uint32_t temp;
  226. struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
  227. /* Configure interface. */
  228. setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
  229. /* Wait for clock to stabilize */
  230. do {
  231. temp = __raw_readl(&ehci->control);
  232. udelay(1000);
  233. } while (!(temp & PHY_CLK_VALID));
  234. #endif
  235. }
  236. int cpu_init_r (void)
  237. {
  238. #ifdef CONFIG_QE
  239. uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
  240. qe_init(qe_base);
  241. qe_reset();
  242. #endif
  243. return 0;
  244. }
  245. /*
  246. * Print out the bus arbiter event
  247. */
  248. #if defined(CONFIG_DISPLAY_AER_FULL)
  249. static int print_83xx_arb_event(int force)
  250. {
  251. static char* event[] = {
  252. "Address Time Out",
  253. "Data Time Out",
  254. "Address Only Transfer Type",
  255. "External Control Word Transfer Type",
  256. "Reserved Transfer Type",
  257. "Transfer Error",
  258. "reserved",
  259. "reserved"
  260. };
  261. static char* master[] = {
  262. "e300 Core Data Transaction",
  263. "reserved",
  264. "e300 Core Instruction Fetch",
  265. "reserved",
  266. "TSEC1",
  267. "TSEC2",
  268. "USB MPH",
  269. "USB DR",
  270. "Encryption Core",
  271. "I2C Boot Sequencer",
  272. "JTAG",
  273. "reserved",
  274. "eSDHC",
  275. "PCI1",
  276. "PCI2",
  277. "DMA",
  278. "QUICC Engine 00",
  279. "QUICC Engine 01",
  280. "QUICC Engine 10",
  281. "QUICC Engine 11",
  282. "reserved",
  283. "reserved",
  284. "reserved",
  285. "reserved",
  286. "SATA1",
  287. "SATA2",
  288. "SATA3",
  289. "SATA4",
  290. "reserved",
  291. "PCI Express 1",
  292. "PCI Express 2",
  293. "TDM-DMAC"
  294. };
  295. static char *transfer[] = {
  296. "Address-only, Clean Block",
  297. "Address-only, lwarx reservation set",
  298. "Single-beat or Burst write",
  299. "reserved",
  300. "Address-only, Flush Block",
  301. "reserved",
  302. "Burst write",
  303. "reserved",
  304. "Address-only, sync",
  305. "Address-only, tlbsync",
  306. "Single-beat or Burst read",
  307. "Single-beat or Burst read",
  308. "Address-only, Kill Block",
  309. "Address-only, icbi",
  310. "Burst read",
  311. "reserved",
  312. "Address-only, eieio",
  313. "reserved",
  314. "Single-beat write",
  315. "reserved",
  316. "ecowx - Illegal single-beat write",
  317. "reserved",
  318. "reserved",
  319. "reserved",
  320. "Address-only, TLB Invalidate",
  321. "reserved",
  322. "Single-beat or Burst read",
  323. "reserved",
  324. "eciwx - Illegal single-beat read",
  325. "reserved",
  326. "Burst read",
  327. "reserved"
  328. };
  329. int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
  330. >> AEATR_EVENT_SHIFT;
  331. int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
  332. >> AEATR_MSTR_ID_SHIFT;
  333. int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
  334. >> AEATR_TBST_SHIFT;
  335. int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
  336. >> AEATR_TSIZE_SHIFT;
  337. int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
  338. >> AEATR_TTYPE_SHIFT;
  339. if (!force && !gd->arch.arbiter_event_address)
  340. return 0;
  341. puts("Arbiter Event Status:\n");
  342. printf(" Event Address: 0x%08lX\n",
  343. gd->arch.arbiter_event_address);
  344. printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
  345. printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
  346. printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
  347. tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
  348. printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
  349. return gd->arch.arbiter_event_address;
  350. }
  351. #elif defined(CONFIG_DISPLAY_AER_BRIEF)
  352. static int print_83xx_arb_event(int force)
  353. {
  354. if (!force && !gd->arch.arbiter_event_address)
  355. return 0;
  356. printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
  357. gd->arch.arbiter_event_attributes,
  358. gd->arch.arbiter_event_address);
  359. return gd->arch.arbiter_event_address;
  360. }
  361. #endif /* CONFIG_DISPLAY_AER_xxxx */
  362. #ifndef CONFIG_CPU_MPC83XX
  363. /*
  364. * Figure out the cause of the reset
  365. */
  366. int prt_83xx_rsr(void)
  367. {
  368. static struct {
  369. ulong mask;
  370. char *desc;
  371. } bits[] = {
  372. {
  373. RSR_SWSR, "Software Soft"}, {
  374. RSR_SWHR, "Software Hard"}, {
  375. RSR_JSRS, "JTAG Soft"}, {
  376. RSR_CSHR, "Check Stop"}, {
  377. RSR_SWRS, "Software Watchdog"}, {
  378. RSR_BMRS, "Bus Monitor"}, {
  379. RSR_SRS, "External/Internal Soft"}, {
  380. RSR_HRS, "External/Internal Hard"}
  381. };
  382. static int n = ARRAY_SIZE(bits);
  383. ulong rsr = gd->arch.reset_status;
  384. int i;
  385. char *sep;
  386. puts("Reset Status:");
  387. sep = " ";
  388. for (i = 0; i < n; i++)
  389. if (rsr & bits[i].mask) {
  390. printf("%s%s", sep, bits[i].desc);
  391. sep = ", ";
  392. }
  393. puts("\n");
  394. #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
  395. print_83xx_arb_event(rsr & RSR_BMRS);
  396. #endif
  397. puts("\n");
  398. return 0;
  399. }
  400. #endif