cpu.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  4. */
  5. /*
  6. * CPU specific code for the MPC83xx family.
  7. *
  8. * Derived from the MPC8260 and MPC85xx.
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <irq_func.h>
  13. #include <net.h>
  14. #include <time.h>
  15. #include <vsprintf.h>
  16. #include <watchdog.h>
  17. #include <command.h>
  18. #include <mpc83xx.h>
  19. #include <asm/processor.h>
  20. #include <linux/delay.h>
  21. #include <linux/libfdt.h>
  22. #include <tsec.h>
  23. #include <netdev.h>
  24. #include <fsl_esdhc.h>
  25. #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
  26. #include <linux/immap_qe.h>
  27. #include <asm/io.h>
  28. #endif
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #ifndef CONFIG_CPU_MPC83XX
  31. int checkcpu(void)
  32. {
  33. volatile immap_t *immr;
  34. ulong clock = gd->cpu_clk;
  35. u32 pvr = get_pvr();
  36. u32 spridr;
  37. char buf[32];
  38. int ret;
  39. int i;
  40. const struct cpu_type {
  41. char name[15];
  42. u32 partid;
  43. } cpu_type_list [] = {
  44. CPU_TYPE_ENTRY(8308),
  45. CPU_TYPE_ENTRY(8309),
  46. CPU_TYPE_ENTRY(8311),
  47. CPU_TYPE_ENTRY(8313),
  48. CPU_TYPE_ENTRY(8314),
  49. CPU_TYPE_ENTRY(8315),
  50. CPU_TYPE_ENTRY(8321),
  51. CPU_TYPE_ENTRY(8323),
  52. CPU_TYPE_ENTRY(8343),
  53. CPU_TYPE_ENTRY(8347_TBGA_),
  54. CPU_TYPE_ENTRY(8347_PBGA_),
  55. CPU_TYPE_ENTRY(8349),
  56. CPU_TYPE_ENTRY(8358_TBGA_),
  57. CPU_TYPE_ENTRY(8358_PBGA_),
  58. CPU_TYPE_ENTRY(8360),
  59. CPU_TYPE_ENTRY(8377),
  60. CPU_TYPE_ENTRY(8378),
  61. CPU_TYPE_ENTRY(8379),
  62. };
  63. immr = (immap_t *)CONFIG_SYS_IMMR;
  64. ret = prt_83xx_rsr();
  65. if (ret)
  66. return ret;
  67. puts("CPU: ");
  68. switch (pvr & 0xffff0000) {
  69. case PVR_E300C1:
  70. printf("e300c1, ");
  71. break;
  72. case PVR_E300C2:
  73. printf("e300c2, ");
  74. break;
  75. case PVR_E300C3:
  76. printf("e300c3, ");
  77. break;
  78. case PVR_E300C4:
  79. printf("e300c4, ");
  80. break;
  81. default:
  82. printf("Unknown core, ");
  83. }
  84. spridr = immr->sysconf.spridr;
  85. for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  86. if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
  87. puts("MPC");
  88. puts(cpu_type_list[i].name);
  89. if (IS_E_PROCESSOR(spridr))
  90. puts("E");
  91. if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
  92. SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
  93. REVID_MAJOR(spridr) >= 2)
  94. puts("A");
  95. printf(", Rev: %d.%d", REVID_MAJOR(spridr),
  96. REVID_MINOR(spridr));
  97. break;
  98. }
  99. if (i == ARRAY_SIZE(cpu_type_list))
  100. printf("(SPRIDR %08x unknown), ", spridr);
  101. printf(" at %s MHz, ", strmhz(buf, clock));
  102. printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
  103. return 0;
  104. }
  105. #endif
  106. #ifndef CONFIG_SYSRESET
  107. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  108. {
  109. ulong msr;
  110. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  111. puts("Resetting the board.\n");
  112. /* Interrupts and MMU off */
  113. msr = mfmsr();
  114. msr &= ~(MSR_EE | MSR_IR | MSR_DR);
  115. mtmsr(msr);
  116. /* enable Reset Control Reg */
  117. immap->reset.rpr = 0x52535445;
  118. sync();
  119. isync();
  120. /* confirm Reset Control Reg is enabled */
  121. while(!((immap->reset.rcer) & RCER_CRE))
  122. ;
  123. udelay(200);
  124. /* perform reset, only one bit */
  125. immap->reset.rcr = RCR_SWHR;
  126. return 1;
  127. }
  128. #endif
  129. /*
  130. * Get timebase clock frequency (like cpu_clk in Hz)
  131. */
  132. #ifndef CONFIG_TIMER
  133. unsigned long get_tbclk(void)
  134. {
  135. return (gd->bus_clk + 3L) / 4L;
  136. }
  137. #endif
  138. #if defined(CONFIG_WATCHDOG)
  139. void watchdog_reset (void)
  140. {
  141. int re_enable = disable_interrupts();
  142. /* Reset the 83xx watchdog */
  143. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  144. immr->wdt.swsrr = 0x556c;
  145. immr->wdt.swsrr = 0xaa39;
  146. if (re_enable)
  147. enable_interrupts();
  148. }
  149. #endif
  150. #ifndef CONFIG_DM_ETH
  151. /*
  152. * Initializes on-chip ethernet controllers.
  153. * to override, implement board_eth_init()
  154. */
  155. int cpu_eth_init(struct bd_info *bis)
  156. {
  157. #if defined(CONFIG_UEC_ETH)
  158. uec_standard_init(bis);
  159. #endif
  160. #if defined(CONFIG_TSEC_ENET)
  161. tsec_standard_init(bis);
  162. #endif
  163. return 0;
  164. }
  165. #endif /* !CONFIG_DM_ETH */
  166. /*
  167. * Initializes on-chip MMC controllers.
  168. * to override, implement board_mmc_init()
  169. */
  170. int cpu_mmc_init(struct bd_info *bis)
  171. {
  172. #ifdef CONFIG_FSL_ESDHC
  173. return fsl_esdhc_mmc_init(bis);
  174. #else
  175. return 0;
  176. #endif
  177. }
  178. void ppcDWstore(unsigned int *addr, unsigned int *value)
  179. {
  180. asm("lfd 1, 0(%1)\n\t"
  181. "stfd 1, 0(%0)"
  182. :
  183. : "r" (addr), "r" (value)
  184. : "memory");
  185. }
  186. void ppcDWload(unsigned int *addr, unsigned int *ret)
  187. {
  188. asm("lfd 1, 0(%0)\n\t"
  189. "stfd 1, 0(%1)"
  190. :
  191. : "r" (addr), "r" (ret)
  192. : "memory");
  193. }