cache.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <asm/immap.h>
  9. #include <asm/cache.h>
  10. volatile int *cf_icache_status = (int *)ICACHE_STATUS;
  11. volatile int *cf_dcache_status = (int *)DCACHE_STATUS;
  12. void flush_cache(ulong start_addr, ulong size)
  13. {
  14. /* Must be implemented for all M68k processors with copy-back data cache */
  15. }
  16. int icache_status(void)
  17. {
  18. return *cf_icache_status;
  19. }
  20. int dcache_status(void)
  21. {
  22. return *cf_dcache_status;
  23. }
  24. void icache_enable(void)
  25. {
  26. icache_invalid();
  27. *cf_icache_status = 1;
  28. #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
  29. __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
  30. __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
  31. #if defined(CONFIG_CF_V4E)
  32. __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
  33. __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
  34. #endif
  35. #else
  36. __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
  37. __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
  38. #endif
  39. __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
  40. }
  41. void icache_disable(void)
  42. {
  43. u32 temp = 0;
  44. *cf_icache_status = 0;
  45. icache_invalid();
  46. #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
  47. __asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
  48. __asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
  49. #if defined(CONFIG_CF_V4E)
  50. __asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
  51. __asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
  52. #endif
  53. #else
  54. __asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
  55. __asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
  56. #endif
  57. }
  58. void icache_invalid(void)
  59. {
  60. u32 temp;
  61. temp = CONFIG_SYS_ICACHE_INV;
  62. if (*cf_icache_status)
  63. temp |= CONFIG_SYS_CACHE_ICACR;
  64. __asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
  65. }
  66. /*
  67. * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
  68. * the dcache will be dummy in ColdFire V2 and V3
  69. */
  70. void dcache_enable(void)
  71. {
  72. dcache_invalid();
  73. *cf_dcache_status = 1;
  74. #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
  75. __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
  76. __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
  77. #if defined(CONFIG_CF_V4E)
  78. __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
  79. __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
  80. #endif
  81. #endif
  82. __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
  83. }
  84. void dcache_disable(void)
  85. {
  86. u32 temp = 0;
  87. *cf_dcache_status = 0;
  88. dcache_invalid();
  89. __asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
  90. #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
  91. __asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
  92. __asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
  93. #if defined(CONFIG_CF_V4E)
  94. __asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
  95. __asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
  96. #endif
  97. #endif
  98. }
  99. void dcache_invalid(void)
  100. {
  101. #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
  102. u32 temp;
  103. temp = CONFIG_SYS_DCACHE_INV;
  104. if (*cf_dcache_status)
  105. temp |= CONFIG_SYS_CACHE_DCACR;
  106. if (*cf_icache_status)
  107. temp |= CONFIG_SYS_CACHE_ICACR;
  108. __asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
  109. #endif
  110. }
  111. __weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
  112. {
  113. /* An empty stub, real implementation should be in platform code */
  114. }
  115. __weak void flush_dcache_range(unsigned long start, unsigned long stop)
  116. {
  117. /* An empty stub, real implementation should be in platform code */
  118. }