cpu.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Josef Baumgartner <josef.baumgartner@telex.de>
  5. *
  6. * MCF5282 additionals
  7. * (C) Copyright 2005
  8. * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
  9. *
  10. * MCF5275 additions
  11. * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  12. *
  13. * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
  14. */
  15. #include <common.h>
  16. #include <init.h>
  17. #include <net.h>
  18. #include <vsprintf.h>
  19. #include <watchdog.h>
  20. #include <command.h>
  21. #include <asm/immap.h>
  22. #include <asm/io.h>
  23. #include <netdev.h>
  24. #include <linux/delay.h>
  25. #include "cpu.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #ifdef CONFIG_M5208
  28. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  29. {
  30. rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  31. udelay(1000);
  32. out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  33. /* we don't return! */
  34. return 0;
  35. };
  36. #if defined(CONFIG_DISPLAY_CPUINFO)
  37. int print_cpuinfo(void)
  38. {
  39. char buf1[32], buf2[32];
  40. printf("CPU: Freescale Coldfire MCF5208\n"
  41. " CPU CLK %s MHz BUS CLK %s MHz\n",
  42. strmhz(buf1, gd->cpu_clk),
  43. strmhz(buf2, gd->bus_clk));
  44. return 0;
  45. };
  46. #endif /* CONFIG_DISPLAY_CPUINFO */
  47. #if defined(CONFIG_WATCHDOG)
  48. /* Called by macro WATCHDOG_RESET */
  49. void watchdog_reset(void)
  50. {
  51. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  52. out_be16(&wdt->sr, 0x5555);
  53. out_be16(&wdt->sr, 0xaaaa);
  54. }
  55. int watchdog_disable(void)
  56. {
  57. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  58. /* reset watchdog counter */
  59. out_be16(&wdt->sr, 0x5555);
  60. out_be16(&wdt->sr, 0xaaaa);
  61. /* disable watchdog timer */
  62. out_be16(&wdt->cr, 0);
  63. puts("WATCHDOG:disabled\n");
  64. return (0);
  65. }
  66. int watchdog_init(void)
  67. {
  68. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  69. /* disable watchdog */
  70. out_be16(&wdt->cr, 0);
  71. /* set timeout and enable watchdog */
  72. out_be16(&wdt->mr,
  73. (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  74. /* reset watchdog counter */
  75. out_be16(&wdt->sr, 0x5555);
  76. out_be16(&wdt->sr, 0xaaaa);
  77. puts("WATCHDOG:enabled\n");
  78. return (0);
  79. }
  80. #endif /* #ifdef CONFIG_WATCHDOG */
  81. #endif /* #ifdef CONFIG_M5208 */
  82. #ifdef CONFIG_M5271
  83. #if defined(CONFIG_DISPLAY_CPUINFO)
  84. /*
  85. * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
  86. * determine which one we are running on, based on the Chip Identification
  87. * Register (CIR).
  88. */
  89. int print_cpuinfo(void)
  90. {
  91. char buf[32];
  92. unsigned short cir; /* Chip Identification Register */
  93. unsigned short pin; /* Part identification number */
  94. unsigned char prn; /* Part revision number */
  95. char *cpu_model;
  96. cir = mbar_readShort(MCF_CCM_CIR);
  97. pin = cir >> MCF_CCM_CIR_PIN_LEN;
  98. prn = cir & MCF_CCM_CIR_PRN_MASK;
  99. switch (pin) {
  100. case MCF_CCM_CIR_PIN_MCF5270:
  101. cpu_model = "5270";
  102. break;
  103. case MCF_CCM_CIR_PIN_MCF5271:
  104. cpu_model = "5271";
  105. break;
  106. default:
  107. cpu_model = NULL;
  108. break;
  109. }
  110. if (cpu_model)
  111. printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
  112. cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
  113. else
  114. printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
  115. " (PIN: 0x%x) rev. %hu, at %s MHz\n",
  116. pin, prn, strmhz(buf, CONFIG_SYS_CLK));
  117. return 0;
  118. }
  119. #endif /* CONFIG_DISPLAY_CPUINFO */
  120. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  121. {
  122. /* Call the board specific reset actions first. */
  123. if(board_reset) {
  124. board_reset();
  125. }
  126. mbar_writeByte(MCF_RCM_RCR,
  127. MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
  128. return 0;
  129. };
  130. #if defined(CONFIG_WATCHDOG)
  131. void watchdog_reset(void)
  132. {
  133. mbar_writeShort(MCF_WTM_WSR, 0x5555);
  134. mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
  135. }
  136. int watchdog_disable(void)
  137. {
  138. mbar_writeShort(MCF_WTM_WCR, 0);
  139. return (0);
  140. }
  141. int watchdog_init(void)
  142. {
  143. mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
  144. return (0);
  145. }
  146. #endif /* #ifdef CONFIG_WATCHDOG */
  147. #endif
  148. #ifdef CONFIG_M5272
  149. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  150. {
  151. wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
  152. out_be16(&wdp->wdog_wrrr, 0);
  153. udelay(1000);
  154. /* enable watchdog, set timeout to 0 and wait */
  155. out_be16(&wdp->wdog_wrrr, 1);
  156. while (1) ;
  157. /* we don't return! */
  158. return 0;
  159. };
  160. #if defined(CONFIG_DISPLAY_CPUINFO)
  161. int print_cpuinfo(void)
  162. {
  163. sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
  164. uchar msk;
  165. char *suf;
  166. puts("CPU: ");
  167. msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
  168. switch (msk) {
  169. case 0x2:
  170. suf = "1K75N";
  171. break;
  172. case 0x4:
  173. suf = "3K75N";
  174. break;
  175. default:
  176. suf = NULL;
  177. printf("Freescale MCF5272 (Mask:%01x)\n", msk);
  178. break;
  179. }
  180. if (suf)
  181. printf("Freescale MCF5272 %s\n", suf);
  182. return 0;
  183. };
  184. #endif /* CONFIG_DISPLAY_CPUINFO */
  185. #if defined(CONFIG_WATCHDOG)
  186. /* Called by macro WATCHDOG_RESET */
  187. void watchdog_reset(void)
  188. {
  189. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  190. out_be16(&wdt->wdog_wcr, 0);
  191. }
  192. int watchdog_disable(void)
  193. {
  194. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  195. /* reset watchdog counter */
  196. out_be16(&wdt->wdog_wcr, 0);
  197. /* disable watchdog interrupt */
  198. out_be16(&wdt->wdog_wirr, 0);
  199. /* disable watchdog timer */
  200. out_be16(&wdt->wdog_wrrr, 0);
  201. puts("WATCHDOG:disabled\n");
  202. return (0);
  203. }
  204. int watchdog_init(void)
  205. {
  206. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  207. /* disable watchdog interrupt */
  208. out_be16(&wdt->wdog_wirr, 0);
  209. /* set timeout and enable watchdog */
  210. out_be16(&wdt->wdog_wrrr,
  211. (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  212. /* reset watchdog counter */
  213. out_be16(&wdt->wdog_wcr, 0);
  214. puts("WATCHDOG:enabled\n");
  215. return (0);
  216. }
  217. #endif /* #ifdef CONFIG_WATCHDOG */
  218. #endif /* #ifdef CONFIG_M5272 */
  219. #ifdef CONFIG_M5275
  220. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  221. {
  222. rcm_t *rcm = (rcm_t *)(MMAP_RCM);
  223. udelay(1000);
  224. out_8(&rcm->rcr, RCM_RCR_SOFTRST);
  225. /* we don't return! */
  226. return 0;
  227. };
  228. #if defined(CONFIG_DISPLAY_CPUINFO)
  229. int print_cpuinfo(void)
  230. {
  231. char buf[32];
  232. printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
  233. strmhz(buf, CONFIG_SYS_CLK));
  234. return 0;
  235. };
  236. #endif /* CONFIG_DISPLAY_CPUINFO */
  237. #if defined(CONFIG_WATCHDOG)
  238. /* Called by macro WATCHDOG_RESET */
  239. void watchdog_reset(void)
  240. {
  241. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  242. out_be16(&wdt->wsr, 0x5555);
  243. out_be16(&wdt->wsr, 0xaaaa);
  244. }
  245. int watchdog_disable(void)
  246. {
  247. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  248. /* reset watchdog counter */
  249. out_be16(&wdt->wsr, 0x5555);
  250. out_be16(&wdt->wsr, 0xaaaa);
  251. /* disable watchdog timer */
  252. out_be16(&wdt->wcr, 0);
  253. puts("WATCHDOG:disabled\n");
  254. return (0);
  255. }
  256. int watchdog_init(void)
  257. {
  258. wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
  259. /* disable watchdog */
  260. out_be16(&wdt->wcr, 0);
  261. /* set timeout and enable watchdog */
  262. out_be16(&wdt->wmr,
  263. (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
  264. /* reset watchdog counter */
  265. out_be16(&wdt->wsr, 0x5555);
  266. out_be16(&wdt->wsr, 0xaaaa);
  267. puts("WATCHDOG:enabled\n");
  268. return (0);
  269. }
  270. #endif /* #ifdef CONFIG_WATCHDOG */
  271. #endif /* #ifdef CONFIG_M5275 */
  272. #ifdef CONFIG_M5282
  273. #if defined(CONFIG_DISPLAY_CPUINFO)
  274. int print_cpuinfo(void)
  275. {
  276. unsigned char resetsource = MCFRESET_RSR;
  277. printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
  278. MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
  279. printf("Reset:%s%s%s%s%s%s%s\n",
  280. (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
  281. (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
  282. (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
  283. (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
  284. (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
  285. (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
  286. (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
  287. return 0;
  288. }
  289. #endif /* CONFIG_DISPLAY_CPUINFO */
  290. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  291. {
  292. MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
  293. return 0;
  294. };
  295. #endif
  296. #ifdef CONFIG_M5249
  297. #if defined(CONFIG_DISPLAY_CPUINFO)
  298. int print_cpuinfo(void)
  299. {
  300. char buf[32];
  301. printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
  302. strmhz(buf, CONFIG_SYS_CLK));
  303. return 0;
  304. }
  305. #endif /* CONFIG_DISPLAY_CPUINFO */
  306. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  307. {
  308. /* enable watchdog, set timeout to 0 and wait */
  309. mbar_writeByte(MCFSIM_SYPCR, 0xc0);
  310. while (1) ;
  311. /* we don't return! */
  312. return 0;
  313. };
  314. #endif
  315. #ifdef CONFIG_M5253
  316. #if defined(CONFIG_DISPLAY_CPUINFO)
  317. int print_cpuinfo(void)
  318. {
  319. char buf[32];
  320. unsigned char resetsource = mbar_readLong(SIM_RSR);
  321. printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
  322. strmhz(buf, CONFIG_SYS_CLK));
  323. if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
  324. printf("Reset:%s%s\n",
  325. (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
  326. : "",
  327. (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
  328. "");
  329. }
  330. return 0;
  331. }
  332. #endif /* CONFIG_DISPLAY_CPUINFO */
  333. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  334. {
  335. /* enable watchdog, set timeout to 0 and wait */
  336. mbar_writeByte(SIM_SYPCR, 0xc0);
  337. while (1) ;
  338. /* we don't return! */
  339. return 0;
  340. };
  341. #endif
  342. #if defined(CONFIG_MCFFEC)
  343. /* Default initializations for MCFFEC controllers. To override,
  344. * create a board-specific function called:
  345. * int board_eth_init(bd_t *bis)
  346. */
  347. int cpu_eth_init(struct bd_info *bis)
  348. {
  349. return mcffec_initialize(bis);
  350. }
  351. #endif