cpu_init.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2000-2003
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
  8. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <init.h>
  13. #include <watchdog.h>
  14. #include <asm/immap.h>
  15. #include <asm/io.h>
  16. #if defined(CONFIG_CMD_NET)
  17. #include <config.h>
  18. #include <net.h>
  19. #include <asm/fec.h>
  20. #endif
  21. /* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */
  22. #ifdef CONFIG_M5235
  23. #define out_be_fbcs_reg out_be16
  24. #else
  25. #define out_be_fbcs_reg out_be32
  26. #endif
  27. /*
  28. * Breath some life into the CPU...
  29. *
  30. * Set up the memory map,
  31. * initialize a bunch of registers,
  32. * initialize the UPM's
  33. */
  34. void cpu_init_f(void)
  35. {
  36. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  37. fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  38. wdog_t *wdog = (wdog_t *) MMAP_WDOG;
  39. scm_t *scm = (scm_t *) MMAP_SCM;
  40. /* watchdog is enabled by default - disable the watchdog */
  41. #ifndef CONFIG_WATCHDOG
  42. out_be16(&wdog->cr, 0);
  43. #endif
  44. out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
  45. /* Port configuration */
  46. out_8(&gpio->par_cs, 0);
  47. #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  48. out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  49. out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  50. out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  51. #endif
  52. #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  53. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
  54. out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  55. out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  56. out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  57. #endif
  58. #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  59. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
  60. out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  61. out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  62. out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  63. #endif
  64. #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  65. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
  66. out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  67. out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  68. out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  69. #endif
  70. #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  71. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
  72. out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  73. out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  74. out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  75. #endif
  76. #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
  77. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
  78. out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  79. out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  80. out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  81. #endif
  82. #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
  83. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
  84. out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
  85. out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
  86. out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
  87. #endif
  88. #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
  89. setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
  90. out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
  91. out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
  92. out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
  93. #endif
  94. #ifdef CONFIG_SYS_I2C_FSL
  95. CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
  96. CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
  97. #endif
  98. icache_enable();
  99. }
  100. /*
  101. * initialize higher level parts of CPU like timers
  102. */
  103. int cpu_init_r(void)
  104. {
  105. return (0);
  106. }
  107. void uart_port_conf(int port)
  108. {
  109. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  110. /* Setup Ports: */
  111. switch (port) {
  112. case 0:
  113. clrbits_be16(&gpio->par_uart,
  114. GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
  115. setbits_be16(&gpio->par_uart,
  116. GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
  117. break;
  118. case 1:
  119. clrbits_be16(&gpio->par_uart,
  120. GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
  121. setbits_be16(&gpio->par_uart,
  122. GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
  123. break;
  124. case 2:
  125. #ifdef CONFIG_SYS_UART2_PRI_GPIO
  126. clrbits_be16(&gpio->par_uart,
  127. GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
  128. setbits_be16(&gpio->par_uart,
  129. GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
  130. #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
  131. clrbits_8(&gpio->par_feci2c,
  132. GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
  133. setbits_8(&gpio->par_feci2c,
  134. GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
  135. #endif
  136. break;
  137. }
  138. }
  139. #if defined(CONFIG_CMD_NET)
  140. int fecpin_setclear(fec_info_t *info, int setclear)
  141. {
  142. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  143. if (setclear) {
  144. setbits_8(&gpio->par_feci2c,
  145. GPIO_PAR_FECI2C_EMDC_FECEMDC |
  146. GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
  147. } else {
  148. clrbits_8(&gpio->par_feci2c,
  149. GPIO_PAR_FECI2C_EMDC_MASK |
  150. GPIO_PAR_FECI2C_EMDIO_MASK);
  151. }
  152. return 0;
  153. }
  154. #endif