sc-regs.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * UniPhier SC (System Control) block registers
  4. *
  5. * Copyright (C) 2011-2015 Panasonic Corporation
  6. * Copyright (C) 2015-2016 Socionext Inc.
  7. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  8. */
  9. #ifndef ARCH_SC_REGS_H
  10. #define ARCH_SC_REGS_H
  11. #ifndef __ASSEMBLY__
  12. #include <linux/compiler.h>
  13. #define sc_base ((void __iomem *)SC_BASE)
  14. #endif
  15. #define SC_BASE 0x61840000
  16. #define SC_DPLLCTRL 0x1200
  17. #define SC_DPLLCTRL_SSC_EN (0x1 << 31)
  18. #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
  19. #define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
  20. #define SC_DPLLCTRL2 0x1204
  21. #define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
  22. #define SC_DPLLCTRL3 0x1208
  23. #define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
  24. #define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
  25. #define SC_UPLLCTRL 0x1210
  26. #define SC_VPLL27ACTRL 0x1270
  27. #define SC_VPLL27ACTRL2 0x1274
  28. #define SC_VPLL27ACTRL3 0x1278
  29. #define SC_VPLL27BCTRL 0x1290
  30. #define SC_VPLL27BCTRL2 0x1294
  31. #define SC_VPLL27BCTRL3 0x1298
  32. #define SC_RSTCTRL 0x2000
  33. #define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
  34. #define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
  35. #define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
  36. #define SC_RSTCTRL_NRST_GIO (0x1 << 6)
  37. /* Pro4 or older */
  38. #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
  39. #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
  40. #define SC_RSTCTRL_NRST_NAND (0x1 << 2)
  41. #define SC_RSTCTRL2 0x2004
  42. #define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
  43. #define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
  44. #define SC_RSTCTRL3 0x2008
  45. /* Pro5 or newer */
  46. #define SC_RSTCTRL4 0x200c
  47. #define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
  48. #define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
  49. #define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
  50. #define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
  51. #define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
  52. #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
  53. #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
  54. #define SC_RSTCTRL5 0x2010
  55. #define SC_RSTCTRL6 0x2014
  56. #define SC_CLKCTRL 0x2104
  57. #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
  58. #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
  59. #define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
  60. #define SC_CLKCTRL_CEN_GIO (0x1 << 6)
  61. /* Pro4 or older */
  62. #define SC_CLKCTRL_CEN_UMC (0x1 << 4)
  63. #define SC_CLKCTRL_CEN_NAND (0x1 << 2)
  64. #define SC_CLKCTRL_CEN_SBC (0x1 << 1)
  65. #define SC_CLKCTRL_CEN_PERI (0x1 << 0)
  66. /* Pro5 or newer */
  67. #define SC_CLKCTRL4 0x210c
  68. #define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
  69. #define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
  70. #define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
  71. #define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
  72. /* System reset control register */
  73. #define SC_IRQTIMSET 0x3000
  74. #define SC_SLFRSTSEL 0x3010
  75. #define SC_SLFRSTCTL 0x3014
  76. #endif /* ARCH_SC_REGS_H */