xusb-padctl-common.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <log.h>
  9. #include "xusb-padctl-common.h"
  10. #include <asm/arch/clock.h>
  11. int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
  12. {
  13. if (phy && phy->ops && phy->ops->prepare)
  14. return phy->ops->prepare(phy);
  15. return phy ? -ENOSYS : -EINVAL;
  16. }
  17. int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
  18. {
  19. if (phy && phy->ops && phy->ops->enable)
  20. return phy->ops->enable(phy);
  21. return phy ? -ENOSYS : -EINVAL;
  22. }
  23. int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
  24. {
  25. if (phy && phy->ops && phy->ops->disable)
  26. return phy->ops->disable(phy);
  27. return phy ? -ENOSYS : -EINVAL;
  28. }
  29. int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
  30. {
  31. if (phy && phy->ops && phy->ops->unprepare)
  32. return phy->ops->unprepare(phy);
  33. return phy ? -ENOSYS : -EINVAL;
  34. }
  35. struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
  36. {
  37. struct tegra_xusb_phy *phy;
  38. int i;
  39. for (i = 0; i < padctl.socdata->num_phys; i++) {
  40. phy = &padctl.socdata->phys[i];
  41. if (phy->type != type)
  42. continue;
  43. return phy;
  44. }
  45. return NULL;
  46. }
  47. static const struct tegra_xusb_padctl_lane *
  48. tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
  49. {
  50. unsigned int i;
  51. for (i = 0; i < padctl->socdata->num_lanes; i++)
  52. if (strcmp(name, padctl->socdata->lanes[i].name) == 0)
  53. return &padctl->socdata->lanes[i];
  54. return NULL;
  55. }
  56. static int
  57. tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
  58. struct tegra_xusb_padctl_group *group,
  59. ofnode node)
  60. {
  61. unsigned int i;
  62. int len, ret;
  63. group->name = ofnode_get_name(node);
  64. len = ofnode_read_string_count(node, "nvidia,lanes");
  65. if (len < 0) {
  66. pr_err("failed to parse \"nvidia,lanes\" property");
  67. return -EINVAL;
  68. }
  69. group->num_pins = len;
  70. for (i = 0; i < group->num_pins; i++) {
  71. ret = ofnode_read_string_index(node, "nvidia,lanes", i,
  72. &group->pins[i]);
  73. if (ret) {
  74. pr_err("failed to read string from \"nvidia,lanes\" property");
  75. return -EINVAL;
  76. }
  77. }
  78. group->num_pins = len;
  79. ret = ofnode_read_string_index(node, "nvidia,function", 0,
  80. &group->func);
  81. if (ret) {
  82. pr_err("failed to parse \"nvidia,func\" property");
  83. return -EINVAL;
  84. }
  85. group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1);
  86. return 0;
  87. }
  88. static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
  89. const char *name)
  90. {
  91. unsigned int i;
  92. for (i = 0; i < padctl->socdata->num_functions; i++)
  93. if (strcmp(name, padctl->socdata->functions[i]) == 0)
  94. return i;
  95. return -ENOENT;
  96. }
  97. static int
  98. tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
  99. const struct tegra_xusb_padctl_lane *lane,
  100. const char *name)
  101. {
  102. unsigned int i;
  103. int func;
  104. func = tegra_xusb_padctl_find_function(padctl, name);
  105. if (func < 0)
  106. return func;
  107. for (i = 0; i < lane->num_funcs; i++)
  108. if (lane->funcs[i] == func)
  109. return i;
  110. return -ENOENT;
  111. }
  112. static int
  113. tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
  114. const struct tegra_xusb_padctl_group *group)
  115. {
  116. unsigned int i;
  117. for (i = 0; i < group->num_pins; i++) {
  118. const struct tegra_xusb_padctl_lane *lane;
  119. unsigned int func;
  120. u32 value;
  121. lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
  122. if (!lane) {
  123. pr_err("no lane for pin %s", group->pins[i]);
  124. continue;
  125. }
  126. func = tegra_xusb_padctl_lane_find_function(padctl, lane,
  127. group->func);
  128. if (func < 0) {
  129. pr_err("function %s invalid for lane %s: %d",
  130. group->func, lane->name, func);
  131. continue;
  132. }
  133. value = padctl_readl(padctl, lane->offset);
  134. /* set pin function */
  135. value &= ~(lane->mask << lane->shift);
  136. value |= func << lane->shift;
  137. /*
  138. * Set IDDQ if supported on the lane and specified in the
  139. * configuration.
  140. */
  141. if (lane->iddq > 0 && group->iddq >= 0) {
  142. if (group->iddq != 0)
  143. value &= ~(1 << lane->iddq);
  144. else
  145. value |= 1 << lane->iddq;
  146. }
  147. padctl_writel(padctl, value, lane->offset);
  148. }
  149. return 0;
  150. }
  151. static int
  152. tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
  153. struct tegra_xusb_padctl_config *config)
  154. {
  155. unsigned int i;
  156. for (i = 0; i < config->num_groups; i++) {
  157. const struct tegra_xusb_padctl_group *group;
  158. int err;
  159. group = &config->groups[i];
  160. err = tegra_xusb_padctl_group_apply(padctl, group);
  161. if (err < 0) {
  162. pr_err("failed to apply group %s: %d",
  163. group->name, err);
  164. continue;
  165. }
  166. }
  167. return 0;
  168. }
  169. static int
  170. tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
  171. struct tegra_xusb_padctl_config *config,
  172. ofnode node)
  173. {
  174. ofnode subnode;
  175. config->name = ofnode_get_name(node);
  176. ofnode_for_each_subnode(subnode, node) {
  177. struct tegra_xusb_padctl_group *group;
  178. int err;
  179. group = &config->groups[config->num_groups];
  180. err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
  181. if (err < 0) {
  182. pr_err("failed to parse group %s", group->name);
  183. return err;
  184. }
  185. config->num_groups++;
  186. }
  187. return 0;
  188. }
  189. static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
  190. ofnode node)
  191. {
  192. ofnode subnode;
  193. int err;
  194. err = ofnode_read_resource(node, 0, &padctl->regs);
  195. if (err < 0) {
  196. pr_err("registers not found");
  197. return err;
  198. }
  199. ofnode_for_each_subnode(subnode, node) {
  200. struct tegra_xusb_padctl_config *config = &padctl->config;
  201. debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode));
  202. err = tegra_xusb_padctl_config_parse_dt(padctl, config,
  203. subnode);
  204. if (err < 0) {
  205. pr_err("failed to parse entry %s: %d",
  206. config->name, err);
  207. continue;
  208. }
  209. }
  210. debug("%s: done\n", __func__);
  211. return 0;
  212. }
  213. struct tegra_xusb_padctl padctl;
  214. int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
  215. const struct tegra_xusb_padctl_soc *socdata)
  216. {
  217. unsigned int i;
  218. int err;
  219. debug("%s: count=%d\n", __func__, count);
  220. for (i = 0; i < count; i++) {
  221. debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np);
  222. if (!ofnode_is_available(nodes[i]))
  223. continue;
  224. padctl.socdata = socdata;
  225. err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
  226. if (err < 0) {
  227. pr_err("failed to parse DT: %d", err);
  228. continue;
  229. }
  230. /* deassert XUSB padctl reset */
  231. reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
  232. err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config);
  233. if (err < 0) {
  234. pr_err("failed to apply pinmux: %d", err);
  235. continue;
  236. }
  237. /* only a single instance is supported */
  238. break;
  239. }
  240. debug("%s: done\n", __func__);
  241. return 0;
  242. }