pmc.c 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <log.h>
  8. #include <linux/arm-smccc.h>
  9. #include <asm/io.h>
  10. #include <asm/arch-tegra/pmc.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
  13. static bool tegra_pmc_detect_tz_only(void)
  14. {
  15. static bool initialized = false;
  16. static bool is_tz_only = false;
  17. u32 value, saved;
  18. if (!initialized) {
  19. saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
  20. value = saved ^ 0xffffffff;
  21. if (value == 0xffffffff)
  22. value = 0xdeadbeef;
  23. /* write pattern and read it back */
  24. writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0);
  25. value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
  26. /* if we read all-zeroes, access is restricted to TZ only */
  27. if (value == 0) {
  28. debug("access to PMC is restricted to TZ\n");
  29. is_tz_only = true;
  30. } else {
  31. /* restore original value */
  32. writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0);
  33. }
  34. initialized = true;
  35. }
  36. return is_tz_only;
  37. }
  38. #endif
  39. uint32_t tegra_pmc_readl(unsigned long offset)
  40. {
  41. #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
  42. if (tegra_pmc_detect_tz_only()) {
  43. struct arm_smccc_res res;
  44. arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
  45. 0, 0, 0, &res);
  46. if (res.a0)
  47. printf("%s(): SMC failed: %lu\n", __func__, res.a0);
  48. return res.a1;
  49. }
  50. #endif
  51. return readl(NV_PA_PMC_BASE + offset);
  52. }
  53. void tegra_pmc_writel(u32 value, unsigned long offset)
  54. {
  55. #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
  56. if (tegra_pmc_detect_tz_only()) {
  57. struct arm_smccc_res res;
  58. arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
  59. value, 0, 0, 0, 0, &res);
  60. if (res.a0)
  61. printf("%s(): SMC failed: %lu\n", __func__, res.a0);
  62. return;
  63. }
  64. #endif
  65. writel(value, NV_PA_PMC_BASE + offset);
  66. }
  67. void reset_cpu(ulong addr)
  68. {
  69. u32 value;
  70. value = tegra_pmc_readl(PMC_CNTRL);
  71. value |= PMC_CNTRL_MAIN_RST;
  72. tegra_pmc_writel(value, PMC_CNTRL);
  73. }