cache.c 925 B

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. /* Tegra cache routines */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch-tegra/ap.h>
  9. #if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL)
  10. #include <asm/arch/gp_padctrl.h>
  11. #endif
  12. #ifndef CONFIG_ARM64
  13. void config_cache(void)
  14. {
  15. u32 reg = 0;
  16. /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
  17. asm volatile(
  18. "mrc p15, 0, r0, c1, c0, 1\n"
  19. "orr r0, r0, #0x41\n"
  20. "mcr p15, 0, r0, c1, c0, 1\n");
  21. /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
  22. if (tegra_get_chip() < CHIPID_TEGRA114)
  23. return;
  24. /*
  25. * Systems with an architectural L2 cache must not use the PL310.
  26. * Config L2CTLR here for a data RAM latency of 3 cycles.
  27. */
  28. asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
  29. reg &= ~7;
  30. reg |= 2;
  31. asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
  32. }
  33. #endif