psci.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <config.h>
  6. #include <common.h>
  7. #include <asm/armv7.h>
  8. #include <asm/cache.h>
  9. #include <asm/gic.h>
  10. #include <asm/io.h>
  11. #include <asm/psci.h>
  12. #include <asm/secure.h>
  13. #include <linux/bitops.h>
  14. #define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xCA7FACE0
  15. #define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xCA7FACE1
  16. #define MPIDR_AFF0 GENMASK(7, 0)
  17. #define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
  18. #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
  19. #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
  20. #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
  21. #define STM32MP1_PSCI_NR_CPUS 2
  22. #if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
  23. #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
  24. #endif
  25. u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = {
  26. PSCI_AFFINITY_LEVEL_ON,
  27. PSCI_AFFINITY_LEVEL_OFF};
  28. static u32 __secure_data cntfrq;
  29. static u32 __secure cp15_read_cntfrq(void)
  30. {
  31. u32 frq;
  32. asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
  33. return frq;
  34. }
  35. static void __secure cp15_write_cntfrq(u32 frq)
  36. {
  37. asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
  38. }
  39. static inline void psci_set_state(int cpu, u8 state)
  40. {
  41. psci_state[cpu] = state;
  42. dsb();
  43. isb();
  44. }
  45. static u32 __secure stm32mp_get_gicd_base_address(void)
  46. {
  47. u32 periphbase;
  48. /* get the GIC base address from the CBAR register */
  49. asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
  50. return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
  51. }
  52. static void __secure stm32mp_raise_sgi0(int cpu)
  53. {
  54. u32 gic_dist_addr;
  55. gic_dist_addr = stm32mp_get_gicd_base_address();
  56. /* ask cpu with SGI0 */
  57. writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR);
  58. }
  59. void __secure psci_arch_cpu_entry(void)
  60. {
  61. u32 cpu = psci_get_cpu_id();
  62. psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
  63. /* write the saved cntfrq */
  64. cp15_write_cntfrq(cntfrq);
  65. /* reset magic in TAMP register */
  66. writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
  67. }
  68. s32 __secure psci_features(u32 function_id, u32 psci_fid)
  69. {
  70. switch (psci_fid) {
  71. case ARM_PSCI_0_2_FN_PSCI_VERSION:
  72. case ARM_PSCI_0_2_FN_CPU_OFF:
  73. case ARM_PSCI_0_2_FN_CPU_ON:
  74. case ARM_PSCI_0_2_FN_AFFINITY_INFO:
  75. case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
  76. case ARM_PSCI_0_2_FN_SYSTEM_OFF:
  77. case ARM_PSCI_0_2_FN_SYSTEM_RESET:
  78. return 0x0;
  79. }
  80. return ARM_PSCI_RET_NI;
  81. }
  82. u32 __secure psci_version(void)
  83. {
  84. return ARM_PSCI_VER_1_0;
  85. }
  86. s32 __secure psci_affinity_info(u32 function_id, u32 target_affinity,
  87. u32 lowest_affinity_level)
  88. {
  89. u32 cpu = target_affinity & MPIDR_AFF0;
  90. if (lowest_affinity_level > 0)
  91. return ARM_PSCI_RET_INVAL;
  92. if (target_affinity & ~MPIDR_AFF0)
  93. return ARM_PSCI_RET_INVAL;
  94. if (cpu >= STM32MP1_PSCI_NR_CPUS)
  95. return ARM_PSCI_RET_INVAL;
  96. return psci_state[cpu];
  97. }
  98. u32 __secure psci_migrate_info_type(void)
  99. {
  100. /*
  101. * in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
  102. * return 2 = Trusted OS is either not present or does not require
  103. * migration, system of this type does not require the caller
  104. * to use the MIGRATE function.
  105. * MIGRATE function calls return NOT_SUPPORTED.
  106. */
  107. return 2;
  108. }
  109. s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
  110. u32 context_id)
  111. {
  112. u32 cpu = target_cpu & MPIDR_AFF0;
  113. if (target_cpu & ~MPIDR_AFF0)
  114. return ARM_PSCI_RET_INVAL;
  115. if (cpu >= STM32MP1_PSCI_NR_CPUS)
  116. return ARM_PSCI_RET_INVAL;
  117. if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
  118. return ARM_PSCI_RET_ALREADY_ON;
  119. /* read and save cntfrq of current cpu to write on target cpu */
  120. cntfrq = cp15_read_cntfrq();
  121. /* reset magic in TAMP register */
  122. if (readl(TAMP_BACKUP_MAGIC_NUMBER))
  123. writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
  124. /*
  125. * ROM code need a first SGI0 after core reset
  126. * core is ready when magic is set to 0 in ROM code
  127. */
  128. while (readl(TAMP_BACKUP_MAGIC_NUMBER))
  129. stm32mp_raise_sgi0(cpu);
  130. /* store target PC and context id*/
  131. psci_save(cpu, pc, context_id);
  132. /* write entrypoint in backup RAM register */
  133. writel((u32)&psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS);
  134. psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
  135. /* write magic number in backup register */
  136. if (cpu == 0x01)
  137. writel(BOOT_API_A7_CORE1_MAGIC_NUMBER,
  138. TAMP_BACKUP_MAGIC_NUMBER);
  139. else
  140. writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
  141. TAMP_BACKUP_MAGIC_NUMBER);
  142. /* Generate an IT to start the core */
  143. stm32mp_raise_sgi0(cpu);
  144. return ARM_PSCI_RET_SUCCESS;
  145. }
  146. s32 __secure psci_cpu_off(void)
  147. {
  148. u32 cpu;
  149. cpu = psci_get_cpu_id();
  150. psci_cpu_off_common();
  151. psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
  152. /* reset core: wfi is managed by BootRom */
  153. if (cpu == 0x01)
  154. writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR);
  155. else
  156. writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR);
  157. /* just waiting reset */
  158. while (1)
  159. wfi();
  160. }
  161. void __secure psci_system_reset(void)
  162. {
  163. /* System reset */
  164. writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR);
  165. /* just waiting reset */
  166. while (1)
  167. wfi();
  168. }
  169. void __secure psci_system_off(void)
  170. {
  171. /* System Off is not managed, waiting user power off
  172. * TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF
  173. */
  174. while (1)
  175. wfi();
  176. }