fdt.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <log.h>
  8. #include <tee.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <dt-bindings/pinctrl/stm32-pinfunc.h>
  11. #include <linux/io.h>
  12. #define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n))
  13. #define ETZPC_DECPROT_NB 6
  14. #define DECPROT_MASK 0x03
  15. #define NB_PROT_PER_REG 0x10
  16. #define DECPROT_NB_BITS 2
  17. #define DECPROT_SECURED 0x00
  18. #define DECPROT_WRITE_SECURE 0x01
  19. #define DECPROT_MCU_ISOLATION 0x02
  20. #define DECPROT_NON_SECURED 0x03
  21. #define ETZPC_RESERVED 0xffffffff
  22. #define STM32_FDCAN_BASE 0x4400e000
  23. #define STM32_CRYP2_BASE 0x4c005000
  24. #define STM32_CRYP1_BASE 0x54001000
  25. #define STM32_GPU_BASE 0x59000000
  26. #define STM32_DSI_BASE 0x5a000000
  27. static const u32 stm32mp1_ip_addr[] = {
  28. 0x5c008000, /* 00 stgenc */
  29. 0x54000000, /* 01 bkpsram */
  30. 0x5c003000, /* 02 iwdg1 */
  31. 0x5c000000, /* 03 usart1 */
  32. 0x5c001000, /* 04 spi6 */
  33. 0x5c002000, /* 05 i2c4 */
  34. ETZPC_RESERVED, /* 06 reserved */
  35. 0x54003000, /* 07 rng1 */
  36. 0x54002000, /* 08 hash1 */
  37. STM32_CRYP1_BASE, /* 09 cryp1 */
  38. 0x5a003000, /* 0A ddrctrl */
  39. 0x5a004000, /* 0B ddrphyc */
  40. 0x5c009000, /* 0C i2c6 */
  41. ETZPC_RESERVED, /* 0D reserved */
  42. ETZPC_RESERVED, /* 0E reserved */
  43. ETZPC_RESERVED, /* 0F reserved */
  44. 0x40000000, /* 10 tim2 */
  45. 0x40001000, /* 11 tim3 */
  46. 0x40002000, /* 12 tim4 */
  47. 0x40003000, /* 13 tim5 */
  48. 0x40004000, /* 14 tim6 */
  49. 0x40005000, /* 15 tim7 */
  50. 0x40006000, /* 16 tim12 */
  51. 0x40007000, /* 17 tim13 */
  52. 0x40008000, /* 18 tim14 */
  53. 0x40009000, /* 19 lptim1 */
  54. 0x4000a000, /* 1A wwdg1 */
  55. 0x4000b000, /* 1B spi2 */
  56. 0x4000c000, /* 1C spi3 */
  57. 0x4000d000, /* 1D spdifrx */
  58. 0x4000e000, /* 1E usart2 */
  59. 0x4000f000, /* 1F usart3 */
  60. 0x40010000, /* 20 uart4 */
  61. 0x40011000, /* 21 uart5 */
  62. 0x40012000, /* 22 i2c1 */
  63. 0x40013000, /* 23 i2c2 */
  64. 0x40014000, /* 24 i2c3 */
  65. 0x40015000, /* 25 i2c5 */
  66. 0x40016000, /* 26 cec */
  67. 0x40017000, /* 27 dac */
  68. 0x40018000, /* 28 uart7 */
  69. 0x40019000, /* 29 uart8 */
  70. ETZPC_RESERVED, /* 2A reserved */
  71. ETZPC_RESERVED, /* 2B reserved */
  72. 0x4001c000, /* 2C mdios */
  73. ETZPC_RESERVED, /* 2D reserved */
  74. ETZPC_RESERVED, /* 2E reserved */
  75. ETZPC_RESERVED, /* 2F reserved */
  76. 0x44000000, /* 30 tim1 */
  77. 0x44001000, /* 31 tim8 */
  78. ETZPC_RESERVED, /* 32 reserved */
  79. 0x44003000, /* 33 usart6 */
  80. 0x44004000, /* 34 spi1 */
  81. 0x44005000, /* 35 spi4 */
  82. 0x44006000, /* 36 tim15 */
  83. 0x44007000, /* 37 tim16 */
  84. 0x44008000, /* 38 tim17 */
  85. 0x44009000, /* 39 spi5 */
  86. 0x4400a000, /* 3A sai1 */
  87. 0x4400b000, /* 3B sai2 */
  88. 0x4400c000, /* 3C sai3 */
  89. 0x4400d000, /* 3D dfsdm */
  90. STM32_FDCAN_BASE, /* 3E tt_fdcan */
  91. ETZPC_RESERVED, /* 3F reserved */
  92. 0x50021000, /* 40 lptim2 */
  93. 0x50022000, /* 41 lptim3 */
  94. 0x50023000, /* 42 lptim4 */
  95. 0x50024000, /* 43 lptim5 */
  96. 0x50027000, /* 44 sai4 */
  97. 0x50025000, /* 45 vrefbuf */
  98. 0x4c006000, /* 46 dcmi */
  99. 0x4c004000, /* 47 crc2 */
  100. 0x48003000, /* 48 adc */
  101. 0x4c002000, /* 49 hash2 */
  102. 0x4c003000, /* 4A rng2 */
  103. STM32_CRYP2_BASE, /* 4B cryp2 */
  104. ETZPC_RESERVED, /* 4C reserved */
  105. ETZPC_RESERVED, /* 4D reserved */
  106. ETZPC_RESERVED, /* 4E reserved */
  107. ETZPC_RESERVED, /* 4F reserved */
  108. ETZPC_RESERVED, /* 50 sram1 */
  109. ETZPC_RESERVED, /* 51 sram2 */
  110. ETZPC_RESERVED, /* 52 sram3 */
  111. ETZPC_RESERVED, /* 53 sram4 */
  112. ETZPC_RESERVED, /* 54 retram */
  113. 0x49000000, /* 55 otg */
  114. 0x48004000, /* 56 sdmmc3 */
  115. 0x48005000, /* 57 dlybsd3 */
  116. 0x48000000, /* 58 dma1 */
  117. 0x48001000, /* 59 dma2 */
  118. 0x48002000, /* 5A dmamux */
  119. 0x58002000, /* 5B fmc */
  120. 0x58003000, /* 5C qspi */
  121. 0x58004000, /* 5D dlybq */
  122. 0x5800a000, /* 5E eth */
  123. ETZPC_RESERVED, /* 5F reserved */
  124. };
  125. /* fdt helper */
  126. static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
  127. {
  128. int node;
  129. fdt_addr_t regs;
  130. for (node = fdt_first_subnode(fdt, offset);
  131. node >= 0;
  132. node = fdt_next_subnode(fdt, node)) {
  133. regs = fdtdec_get_addr(fdt, node, "reg");
  134. if (addr == regs) {
  135. if (fdtdec_get_is_enabled(fdt, node)) {
  136. fdt_status_disabled(fdt, node);
  137. return true;
  138. }
  139. return false;
  140. }
  141. }
  142. return false;
  143. }
  144. static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
  145. {
  146. const u32 *array;
  147. int array_size, i;
  148. int offset, shift;
  149. u32 addr, status, decprot[ETZPC_DECPROT_NB];
  150. array = stm32mp1_ip_addr;
  151. array_size = ARRAY_SIZE(stm32mp1_ip_addr);
  152. for (i = 0; i < ETZPC_DECPROT_NB; i++)
  153. decprot[i] = readl(ETZPC_DECPROT(i));
  154. for (i = 0; i < array_size; i++) {
  155. offset = i / NB_PROT_PER_REG;
  156. shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
  157. status = (decprot[offset] >> shift) & DECPROT_MASK;
  158. addr = array[i];
  159. debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
  160. if (addr == ETZPC_RESERVED ||
  161. status == DECPROT_NON_SECURED)
  162. continue;
  163. if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
  164. printf("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
  165. addr, i, status);
  166. }
  167. return 0;
  168. }
  169. /* deactivate all the cpu except core 0 */
  170. static void stm32_fdt_fixup_cpu(void *blob, char *name)
  171. {
  172. int off;
  173. u32 reg;
  174. off = fdt_path_offset(blob, "/cpus");
  175. if (off < 0) {
  176. printf("%s: couldn't find /cpus node\n", __func__);
  177. return;
  178. }
  179. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  180. while (off != -FDT_ERR_NOTFOUND) {
  181. reg = fdtdec_get_addr(blob, off, "reg");
  182. if (reg != 0) {
  183. fdt_del_node(blob, off);
  184. printf("FDT: cpu %d node remove for %s\n", reg, name);
  185. /* after delete we can't trust the offsets anymore */
  186. off = -1;
  187. }
  188. off = fdt_node_offset_by_prop_value(blob, off,
  189. "device_type", "cpu", 4);
  190. }
  191. }
  192. static void stm32_fdt_disable(void *fdt, int offset, u32 addr,
  193. const char *string, const char *name)
  194. {
  195. if (fdt_disable_subnode_by_address(fdt, offset, addr))
  196. printf("FDT: %s@%08x node disabled for %s\n",
  197. string, addr, name);
  198. }
  199. static void stm32_fdt_disable_optee(void *blob)
  200. {
  201. int off, node;
  202. /* Delete "optee" firmware node */
  203. off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
  204. if (off >= 0 && fdtdec_get_is_enabled(blob, off))
  205. fdt_del_node(blob, off);
  206. /* Delete "optee@..." reserved-memory node */
  207. off = fdt_path_offset(blob, "/reserved-memory/");
  208. if (off < 0)
  209. return;
  210. for (node = fdt_first_subnode(blob, off);
  211. node >= 0;
  212. node = fdt_next_subnode(blob, node)) {
  213. if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
  214. continue;
  215. if (fdt_del_node(blob, node))
  216. printf("Failed to remove optee reserved-memory node\n");
  217. }
  218. }
  219. /*
  220. * This function is called right before the kernel is booted. "blob" is the
  221. * device tree that will be passed to the kernel.
  222. */
  223. int ft_system_setup(void *blob, struct bd_info *bd)
  224. {
  225. int ret = 0;
  226. int soc;
  227. u32 pkg, cpu;
  228. char name[SOC_NAME_SIZE];
  229. soc = fdt_path_offset(blob, "/soc");
  230. if (soc < 0)
  231. return soc;
  232. if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
  233. ret = stm32_fdt_fixup_etzpc(blob, soc);
  234. if (ret)
  235. return ret;
  236. }
  237. /* MPUs Part Numbers and name*/
  238. cpu = get_cpu_type();
  239. get_soc_name(name);
  240. switch (cpu) {
  241. case CPU_STM32MP151Fxx:
  242. case CPU_STM32MP151Dxx:
  243. case CPU_STM32MP151Cxx:
  244. case CPU_STM32MP151Axx:
  245. stm32_fdt_fixup_cpu(blob, name);
  246. /* after cpu delete we can't trust the soc offsets anymore */
  247. soc = fdt_path_offset(blob, "/soc");
  248. stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name);
  249. /* fall through */
  250. case CPU_STM32MP153Fxx:
  251. case CPU_STM32MP153Dxx:
  252. case CPU_STM32MP153Cxx:
  253. case CPU_STM32MP153Axx:
  254. stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name);
  255. stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name);
  256. break;
  257. default:
  258. break;
  259. }
  260. switch (cpu) {
  261. case CPU_STM32MP157Dxx:
  262. case CPU_STM32MP157Axx:
  263. case CPU_STM32MP153Dxx:
  264. case CPU_STM32MP153Axx:
  265. case CPU_STM32MP151Dxx:
  266. case CPU_STM32MP151Axx:
  267. stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name);
  268. stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name);
  269. break;
  270. default:
  271. break;
  272. }
  273. switch (get_cpu_package()) {
  274. case PKG_AA_LBGA448:
  275. pkg = STM32MP_PKG_AA;
  276. break;
  277. case PKG_AB_LBGA354:
  278. pkg = STM32MP_PKG_AB;
  279. break;
  280. case PKG_AC_TFBGA361:
  281. pkg = STM32MP_PKG_AC;
  282. break;
  283. case PKG_AD_TFBGA257:
  284. pkg = STM32MP_PKG_AD;
  285. break;
  286. default:
  287. pkg = 0;
  288. break;
  289. }
  290. if (pkg) {
  291. do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
  292. "st,package", pkg, false);
  293. do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
  294. "st,package", pkg, false);
  295. }
  296. if (!CONFIG_IS_ENABLED(OPTEE) ||
  297. !tee_find_device(NULL, NULL, NULL, NULL))
  298. stm32_fdt_disable_optee(blob);
  299. return ret;
  300. }